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A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs

Hyeonho Song, Jintae Kim, Minjae Lee

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Hyeonho Song
School of Information and Communications, Gwangju Institute of Science and Technology
Jintae Kim
Electronics Engineering Department, Konkuk University
Minjae Lee
School of Information and Communications, Gwangju Institute of Science and Technology

Corresponding author

Keywords:reference buffer,time interleaved ADC,analog to digital converter,pipelined ADC,1.5bit ADC,high PSRR

JOURNALFREE ACCESS

2013 Volume 10Issue 16Pages 20130482

DOIhttps://doi.org/10.1587/elex.10.20130482

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Published: August 25, 2013Received: June 21, 2013Released on J-STAGE: August 25, 2013Accepted: June 28, 2013Advance online publication: July 23, 2013Revised: -

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Article overview

Abstract

A low power reference buffer is proposed to achieve high PSRR and less crosstalk between channels for time-interleaved analog-to-digital converters (ADCs). A conventional approach requires enough bandwidth in feedback amplifiers to suppress high frequency supply noise, which tends to increase power consumption. Furthermore the number of output drivers that share error amplifier output is unavoidably limited due to the coupling across ADC channels. We propose design techniques to improve the corner frequency of power supply rejection ratio (PSRR) by a factor of 100 and the cross-channel isolation by 20dB without drawing more current.

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