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Special Section on Analog Circuit Techniques and Related Topics

The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique

Shoichi HARA, Rui MURAKAMI, Kenichi OKADA, Akira MATSUZAWA

Author information

Shoichi HARA
Department of Physical Electronics, Tokyo Institute of Technology
Rui MURAKAMI
Department of Physical Electronics, Tokyo Institute of Technology
Kenichi OKADA
Department of Physical Electronics, Tokyo Institute of Technology
Akira MATSUZAWA
Department of Physical Electronics, Tokyo Institute of Technology

Corresponding author

Keywords:CMOS,VCO,divider,inductor

JOURNALRESTRICTED ACCESS

2010 Volume E93.AIssue 2Pages 424-430

DOIhttps://doi.org/10.1587/transfun.E93.A.424

Details

Published: February 01, 2010Received: June 18, 2009Available on J-STAGE: February 01, 2010Accepted: -Advance online publication: -Revised: -

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Article overview

Abstract

The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0dBc/Hz of FoM, can be extended from 6.5-12.5GHz to 1.5-12.5GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.

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