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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
Yuchun MAXin LIYu WANGXianlong HONG
Author information
  • Yuchun MA

    Dept. of Computer Science and Technology, TNList, Tsinghua University

  • Xin LI

    Dept. of Computer Science and Technology, TNList, Tsinghua University

  • Yu WANG

    E.E. Dept., TNList, Tsinghua University

  • Xianlong HONG

    Dept. of Computer Science and Technology, TNList, Tsinghua University

Corresponding author

ORCID
Keywords:3D ICs,incremental floorplanning,thermal,MILP
JOURNALRESTRICTED ACCESS

2009 Volume E92.AIssue 12Pages 2979-2989

DOIhttps://doi.org/10.1587/transfun.E92.A.2979
Details
  • Published: December 01, 2009Received: March 19, 2009Available on J-STAGE: December 01, 2009Accepted: -Advance online publication: -Revised: -
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Abstract
In 3D IC design, thermal issue is a critical challenge. To eliminate hotspots, physical layouts are always adjusted by some incremental changes, such as shifting or duplicating hot blocks. In this paper, we distinguish the thermal-aware incremental changes in three different categories: migrating computation, growing unit and moving hotspot blocks. However, these modifications may degrade the packing area as well as interconnect distribution greatly. In this paper, mixed integer linear programming (MILP) models are devised according to these different incremental changes so that multiple objectives can be optimized simultaneously. Furthermore, to avoid random incremental modification, which may be inefficient and need long runtime to converge, here potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks. Still, experimental results also show that the thermal optimization flow can reduce max on-chip temperature by 14% to the initial packings generated by an existing 3D floorplanning tool CBA, and achieve better area and total wirelength improvement than individual operations do. The results with the initial packings from CBA_T (Thermal-aware CBA floorplanner) show that 13.5% temperature reduction can be obtained by our incremental optimization flow.
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© 2009 The Institute of Electronics, Information and Communication Engineers
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