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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC
Takafumi KATAYAMATian SONGWen SHIGen FUJITAXiantao JIANGTakashi SHIMAMOTO
Author information
  • Takafumi KATAYAMA

    Department of Electrical and Electronics Engineering, The University of Tokushima

  • Tian SONG

    Department of Electrical and Electronics Engineering, The University of Tokushima

  • Wen SHI

    Department of Electrical and Electronics Engineering, The University of Tokushima

  • Gen FUJITA

    Department of Engineering Informatics, Osaka Electro-Communication University

  • Xiantao JIANG

    Department of Electrical and Electronics Engineering, The University of Tokushima

  • Takashi SHIMAMOTO

    Department of Electrical and Electronics Engineering, The University of Tokushima

Corresponding author

ORCID
Keywords:high efficiency video coding (HEVC),scalable high efficiency video coding (SHVC),inter layer reference prediction,intra prediction
JOURNALRESTRICTED ACCESS

2017 Volume E100.AIssue 12Pages 2936-2947

DOIhttps://doi.org/10.1587/transfun.E100.A.2936
Details
  • Published: December 01, 2017Manuscript Received: March 14, 2017Released on J-STAGE: December 01, 2017Accepted: -Advance online publication: -Manuscript Revised: August 11, 2017
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Abstract

Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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