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IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Information and Communication System Security
Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor
Jinli RAOTianyong AOShu XUKui DAIXuecheng ZOU
Author information
  • Jinli RAO

    School of Optical and Electronic Information, Huazhong University of Science and Technology

  • Tianyong AO

    School of Physics and Electronics, Henan University

  • Shu XU

    Science and Technology on Information Assurance Laboratory

  • Kui DAI

    Institute of National Network Security and Information, Peking University

  • Xuecheng ZOU

    School of Optical and Electronic Information, Huazhong University of Science and Technology

Corresponding author

ORCID
Keywords:SHA-3,application specific instruction-set processor,RISC-V,IoT
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2018 Volume E101.DIssue 11Pages 2698-2705

DOIhttps://doi.org/10.1587/transinf.2017ICP0019
Details
  • Published: November 01, 2018Manuscript Received: November 14, 2017Released on J-STAGE: November 01, 2018Accepted: -Advance online publication: -Manuscript Revised: April 03, 2018
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Abstract

Data integrity is a key metric of security for Internet of Things (IoT) which refers to accuracy and reliability of data during transmission, storage and retrieval. Cryptographic hash functions are common means used for data integrity verification. Newly announced SHA-3 is the next generation hash function standard to replace existing SHA-1 and SHA-2 standards for better security. However, its underlyingKeccak algorithm is computation intensive and thus limits its deployment on IoT systems which are normally equipped with 32-bit resource constrained embedded processors. This paper proposes two efficient SHA-3 ASIPs based on an open 32-bit RISC-V embedded processor namedZ-scale. The first operation-oriented ASIP (OASIP) focuses on accelerating time-consuming operations with instruction set extensions to improve resource efficiency. And next datapath-oriented ASIP (DASIP) targets exploiting advance data and instruction level parallelism with extended auxiliary registers and customized datapath to achieve high performance. Implementation results show that both proposed ASIPs can effectively accelerate SHA-3 algorithm with 14.6% and 26.9% code size reductions, 30% and 87% resource efficiency improvements, 71% and 262% better maximum throughputs as well as 40% and 288% better power efficiencies than reference design. This work makes SHA-3 algorithm integration practical for both low-cost and high-performance IoT systems.

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© 2018 The Institute of Electronics, Information and Communication Engineers
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