Movatterモバイル変換

• Changyong Liu

  School of Electronics and Information Engineering, Anhui University

• Nianlong Liu

  Water Resources Information Center of Henan

• Zhiting Lin

  School of Electronics and Information Engineering, Anhui University

• Xiulong Wu

  School of Electronics and Information Engineering, Anhui University

• Chunyu Peng

  School of Electronics and Information Engineering, Anhui University

• Qiang Zhao

  School of Electronics and Information Engineering, Anhui University

• Xuan Li

  School of Electronics and Information Engineering, Anhui University

• Junning Chen

  School of Electronics and Information Engineering, Anhui University

• Xuan Zeng

  State Key Laboratory of ASIC & System, Department of Microelectronics, Fudan University

• Xiangdong Hu

  Shanghai High Performance Integrated Circuit Design Center

A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dual-modular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.