Important Information

AMD Vitis™ Unified Software Platform 2025.2 Release Highlights :

Enhanced Design Flow with AMD Versal™ AI Engines 

• AI Engine API enhancements for Versal AI Edge and Versal AI Edge Series Gen 2 (AIE-ML and AIE-ML v2)
  • New and Enhanced Data Types
    • New: Block floating-point MX6
    • New: Block floating-point MX4
    • New: cbfloat16 (emulated)
    • Enhanced: cfloat & cbfloat16 (available in FFT and matrix multiplication functions)
    • Enhanced: cint16 & cint32 (can now use cint16 twiddle types in FFTs)
• Programming Model Updates
  • Create Read-Only Shared Buffer
  • Repeated MEM Tile Read Access (AIE-ML and AIE-ML v2)
  • DMA-FIFO Support in AIE-ML and AIE-ML v2
  • Ping pong buffers can span two adjacent MEM tiles 
  • (AIE-ML & AIE-ML v2)
  • Shared Parameters for Local Tile Memory
  • Packet Switching Enhancements for AIE-ML and AIE-ML v2
• New and enhanced DSP library functions for Versal AI Engines
  • New Cumulative Sum 
  • New Euclidean Distance
  • New Function Approximation (invoked via RTP update or LUT)
  • Enhanced TDM FIR with Packet Switching (saves PLIOs)
  • Enhanced 1D FFT using AIE + PL (reduces PL resources required)
  • Enhanced FIR (throughput optimizations)
• Improved AI Engine mapper and router - compiler will explore different footprints/layouts for more efficient implementation

Easier Verification of Versal AI Engine Designs

• Updates to Vitis Functional Simulation workflow with support for C++ (early access)
• Hardware-in-the-Loop using MATLAB® and Python™ testbench (early access)

Enhancements to Vitis Model Composer for AI Engine DSP Designs

• Ease-of-use updates for Super Sample Rate (SSR) Design Flow with AI Engines (early access)
• Additional blocks available for both AI Engines and HDL:
  • AIE, AIE-ML, AIE-ML v2
    • New: Function Approximation
    • New: Correlation/Convolution
    • New: Cumulative Sum
  • HDL Library Blocks
    • Enhanced: FFT (Added native floating-point SSR = 32, 64)
    • Enhanced: FIR (Support fractional rate interpolation with SSR)

Updates for Vitis IDE for Embedded Development

• Python API for Updating Building Configuration 
• Run Vitis™ API in Python Environment 
• PS Trace Visible by Default for Supported Cores
• Debug Enhancement – Updated values are now highlighted in Watch View and Register view
• Cancel or Terminate Backend Tasks
• Unified Platform BSP File Paths (Linux® & Windows®) 
• Theia AI Integration (Early Access) – Provides the infrastructure for developer to use their preferred LLM and code assistants
• DFX Platform Creation with Python API 
• Backing Up or Sharing a Workspace 
• Enhanced Logging for Config Files 
• New “Integration Project” Component

To install Vitis Core Development Kit, select Vitis on the Unified Installer. Vitis installation includes Vivado™ Design Suite, Vitis Model Composer, Vitis HLS.

There is no need to install Vivado separately.

Important Information

The Vitis™ Embedded Development is a standalone embedded software development package for creating, building, debugging, optimizing, and downloading software applications for AMD FPGA processors. It includes a new Vitis IDE  with its new backend Vitis Server, as well as the classic command line utilities such as hw_server, bootgen and program_flash.

Note: This release supports Versal™, Zynq™ MPSoC, Zynq 7000 and MicroBlaze™.