Multiple hardware versions found.
Performance could vary due to unannounced flash/controller changes.
| Capacity: | 1 TB(1000 GB) |
|---|---|
| Variants: | 480 GB500 GB960 GB1 TB2 TB |
| Hardware Versions: |
|
| Overprovisioning: | 92.7 GB/ 10.0 % |
| Production: | Active |
| Released: | Mar 12th, 2018 |
| Price at Launch: | 78 USD |
| Part Number: | SSD7CS900-1TB-RB |
| Market: | Consumer |
| Form Factor: | 2.5" |
|---|---|
| Interface: | SATA 6 Gbps |
| Protocol: | AHCI |
| Power Draw: | 0.30 W (Idle) 2.0 W (Avg) Unknown (Max) |
| Manufacturer: | Phison |
|---|---|
| Name: | PS3111-S11-13 Find More Drives |
| Architecture: | ARM 32-bit |
| Core Count: | Single-Core |
| Frequency: | 200 MHz |
| Foundry: | UMC |
| Process: | 40 nm |
| Flash Channels: | 2@ 533 MT/s |
| Chip Enables: | 8 |
| Manufacturer: | Micron |
|---|---|
| Name: | B17A FortisFlash |
| Type: | TLC |
| Technology: | 64-layer |
| Speed: | 50 MT/s .. 667 MT/s |
| Capacity: | Unknown |
| ONFI: | 4.0 |
| Topology: | Floating Gate |
| Process: | 20 nm |
| Die Size: | 108 mm² (4.7 Gbit/mm²) |
| Planes per Die: | 4 |
| Decks per Die: | 2 |
| Word Lines: | 74 per NAND String 86.5% Vertical Efficiency |
| Read Time (tR): | 88 µs |
| Program Time (tProg): | 930 µs |
| Block Erase Time (tBERS): | 15 ms |
| Die Read Speed: | 727 MB/s |
| Die Write Speed: | 69 MB/s |
| Endurance: (up to) | 3000 P/E Cycles (40000 in SLC Mode) |
| Page Size: | 16 KB |
| Block Size: | 2304 Pages |
| Plane Size: | 504 Blocks |
| Type: | None |
|---|
| Sequential Read: | 535 MB/s |
|---|---|
| Sequential Write: | 515 MB/s |
| Random Read: | Unknown |
| Random Write: | Unknown |
| Endurance: | 450 TBW |
| Warranty: | 3 Years |
| MTBF: | 2.0 Million Hours |
| Drive Writes Per Day (DWPD): | 0.4 |
| SLC Write Cache: | Yes |
| TRIM: | Yes |
|---|---|
| SMART: | Yes |
| Power Loss Protection: | No |
| Encryption: |
|
| RGB Lighting: | No |
| PS5 Compatible: | No |
Drive:Other variants might feature Micron's 64-Layer N18A FortisFlash or newer 96-Layer QLC/TLC. Controller:In order to improve performance, Phison implemented a way that the controller utilizes it's internal 32 MiB of SRAM as some kind of "Pit-stop" that is allocated for incoming Write request in order to improve performance since it's a very quick to access and fast RAM. This implementation was called Smart Cache Flush. NAND Die:tPROG with some Overhead: ~ 930µs (Avg) |