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Hafiz Hamza AshrafHafiz Hamza Ashrafhafizhamza313@gmail.comhafizhamza313@gmail.com

CharacterizeCharacterize PipelinesPipelines1)1) Hardware or software implementation – pipelining can be implemented inHardware or software implementation – pipelining can be implemented ineither software or hardware.either software or hardware.2)2) Large or Small Scale – Stations in a pipeline can range from simplistic toLarge or Small Scale – Stations in a pipeline can range from simplistic topowerful, and a pipeline can range in length from short to long.powerful, and a pipeline can range in length from short to long.3)3) Synchronous or asynchronous flow – A synchronous pipeline operatesSynchronous or asynchronous flow – A synchronous pipeline operateslike an assembly line: at a given time, each station is processing somelike an assembly line: at a given time, each station is processing someamount of information. A asynchronous pipeline, allow a station toamount of information. A asynchronous pipeline, allow a station toforward information at any time.forward information at any time.4)4) Buffered or unbuffered flow – One stage of pipeline sends data directly toBuffered or unbuffered flow – One stage of pipeline sends data directly toanother one or a buffer is place between each pairs of stages.another one or a buffer is place between each pairs of stages.5)5) Finite Chunks or Continuous Bit Streams – The digital information thatFinite Chunks or Continuous Bit Streams – The digital information thatpasses though a pipeline can consist of a sequence or small data itemspasses though a pipeline can consist of a sequence or small data itemsor an arbitrarily long bit stream.or an arbitrarily long bit stream.6)6) Automatic Data Feed Or Manual Data Feed – Some implementations ofAutomatic Data Feed Or Manual Data Feed – Some implementations ofpipelines use a separate mechanism to move information, and otherpipelines use a separate mechanism to move information, and otherimplementations require each stage to participate in moving information.implementations require each stage to participate in moving information.

What is PipeliningWhat is Pipelining A technique used in advanced microprocessors whereA technique used in advanced microprocessors wherethe microprocessor begins executing a secondthe microprocessor begins executing a secondinstruction before the first has been completed.instruction before the first has been completed.- A Pipeline is a series of stages, where some work isA Pipeline is a series of stages, where some work isdone at each stage. The work is not finished until it hasdone at each stage. The work is not finished until it haspassed through all stages.passed through all stages. With pipelining, the computer architecture allows theWith pipelining, the computer architecture allows thenext instructions to be fetched while the processor isnext instructions to be fetched while the processor isperforming arithmetic operations, holding them in aperforming arithmetic operations, holding them in abuffer close to the processor until each instructionbuffer close to the processor until each instructionoperation can performed.operation can performed.

How Pipelines WorksHow Pipelines Works The pipeline is divided into segments andThe pipeline is divided into segments andeach segment can execute it operationeach segment can execute it operationconcurrently with the other segments.concurrently with the other segments.Once a segment completes an operations,Once a segment completes an operations,it passes the result to the next segment init passes the result to the next segment inthe pipeline and fetches the nextthe pipeline and fetches the nextoperations from the preceding segment.operations from the preceding segment.

Instructions FetchInstructions Fetch The instruction Fetch (IF) stage is responsible forThe instruction Fetch (IF) stage is responsible forobtaining the requested instruction from memory. Theobtaining the requested instruction from memory. Theinstruction and the program counter (which isinstruction and the program counter (which isincremented to the next instruction) are stored in theincremented to the next instruction) are stored in theIF/ID pipeline register as temporary storage so that mayIF/ID pipeline register as temporary storage so that maybe used in the next stage at the start of the next clockbe used in the next stage at the start of the next clockcycle.cycle.

Instruction DecodeInstruction Decode The Instruction Decode (ID) stage is responsible forThe Instruction Decode (ID) stage is responsible fordecoding the instruction and sending out the variousdecoding the instruction and sending out the variouscontrol lines to the other parts of the processor. Thecontrol lines to the other parts of the processor. Theinstruction is sent to the control unit where it is decodedinstruction is sent to the control unit where it is decodedand the registers are fetched from the register file.and the registers are fetched from the register file.

ExecutionExecution The Execution (EX) stage is where any calculations areThe Execution (EX) stage is where any calculations areperformed. The main component in this stage is theperformed. The main component in this stage is theALU. The ALU is made up of arithmetic, logic andALU. The ALU is made up of arithmetic, logic andcapabilities.capabilities.

Memory and IOMemory and IO The Memory and IO (MEM) stage is responsible forThe Memory and IO (MEM) stage is responsible forstoring and loading values to and from memory. It alsostoring and loading values to and from memory. It alsoresponsible for input or output from the processor. If theresponsible for input or output from the processor. If thecurrent instruction is not of Memory or IO type than thecurrent instruction is not of Memory or IO type than theresult from the ALU is passed through to the write backresult from the ALU is passed through to the write backstage.stage.

Write BackWrite Back The Write Back (WB) stage is responsibleThe Write Back (WB) stage is responsiblefor writing the result of a calculation,for writing the result of a calculation,memory access or input into the registermemory access or input into the registerfile.file.

Operation TimingsOperation Timings Estimated timings for each ofEstimated timings for each ofthe stages:the stages:InstructionInstructionFetchFetch2ns2nsInstructionInstructionDecodeDecode1ns1nsExecutionExecution 2ns2nsMemoryMemoryand IOand IO2ns2nsWrite BackWrite Back 1ns1ns

Advantages/DisadvantagesAdvantages/DisadvantagesAdvantages:Advantages: More efficient use of processorMore efficient use of processor Quicker time of execution of large number ofQuicker time of execution of large number ofinstructionsinstructionsDisadvantages:Disadvantages: Pipelining involves adding hardware to the chipPipelining involves adding hardware to the chip Inability to continuously run the pipelineInability to continuously run the pipelineat full speed because of pipeline hazardsat full speed because of pipeline hazardswhich disrupt the smooth execution of thewhich disrupt the smooth execution of thepipeline.pipeline.

Pipeline HazardsPipeline Hazards Data Hazards – an instruction uses the result of theData Hazards – an instruction uses the result of theprevious instruction. A hazard occurs exactly when anprevious instruction. A hazard occurs exactly when aninstruction tries to read a register in its ID stage that aninstruction tries to read a register in its ID stage that anearlier instruction intends to write in its WB stage.earlier instruction intends to write in its WB stage. Control Hazards – the location of an instruction dependsControl Hazards – the location of an instruction dependson previous instructionon previous instruction Structural Hazards – two instructions need to access theStructural Hazards – two instructions need to access thesame resourcesame resource

StallingStalling Stalling involves halting the flow of instructions until theStalling involves halting the flow of instructions until therequired result is ready to be used. However stallingrequired result is ready to be used. However stallingwastes processor time by doing nothing while waitingwastes processor time by doing nothing while waitingfor the result.for the result.

Type of PipeliningType of Pipelining Software PipeliningSoftware Pipelining1) Can Handle Complex Instructions1) Can Handle Complex Instructions2) Allows programs to be reused2) Allows programs to be reused Hardware PipeliningHardware Pipelining1) Help designer manage complexity – a1) Help designer manage complexity – acomplex task can be divided into smaller,complex task can be divided into smaller,more manageable pieces.more manageable pieces.2) Hardware pipelining offers higher2) Hardware pipelining offers higherperformanceperformance

Type of Hardware PipelinesType of Hardware Pipelines Instruction Pipeline -Instruction Pipeline - AnAn instruction pipelineinstruction pipeline is veryis verysimilar to a manufacturing assembly line.similar to a manufacturing assembly line.1st stage receives some parts, performs its assembly task,1st stage receives some parts, performs its assembly task,and passes the results to the second stage;and passes the results to the second stage;2nd stage takes the partially assembled product from the2nd stage takes the partially assembled product from thefirst stage, performs its task, and passes its work to thefirst stage, performs its task, and passes its work to thethird stage;third stage;3rd stage does its work, passing the results to the last3rd stage does its work, passing the results to the laststage, which completes the task and outputs its results.stage, which completes the task and outputs its results. Data Pipeline – data pipeline is designed to pass dataData Pipeline – data pipeline is designed to pass datafrom stage to stage.from stage to stage.

Instruction Pipelines ConflictInstruction Pipelines Conflict It divided into two categories.It divided into two categories. Data ConflictsData Conflicts Branch ConflictsBranch Conflicts When the current instruction changes a register that theWhen the current instruction changes a register that thenext one needed, data conflicts happens.next one needed, data conflicts happens. When the current instruction make a jump, branchWhen the current instruction make a jump, branchconflicts happens.conflicts happens.

ReferencesReferences http://www.cs.sjsu.edu/~lee/cs147/fall2003http://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppt/23147L25Pipelining.ppt http://murray.newcastle.edu.au/users/studhttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.html#s5ents/1999/c9311421/pipe.html#s5

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