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Pipelining and vector processing
The document discusses parallel processing techniques, categorizing computers based on Flynn's classification, which includes SISD, SIMD, MISD, and MIMD structures. It explains pipelining as a method to improve instruction and data processing efficiency through simultaneous operations, and delves into instruction pipelines and vector processing for complex computations. Additionally, the document highlights array processors and their function in enhancing computer performance through parallelism.
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Pipelining and vector processing
- 1. Parallel Processing,Flynn’s Classification ofComputers Pipelining Instruction Pipeline Pipeline Hazards and their solution Array and Vector ProcessingPipelining and VectorProcessing
- 2.Parallel Processing Itrefers to techniques that are used to providesimultaneous data processing. The system may have two or more ALUs to be able toexecute two or more instruction at the same time. The system may have two or more processorsoperating concurrently. It can be achieved by having multiple functionalunits that perform same or different operationsimultaneously.
- 4.Classification There arevariety of ways in which the parallelprocessing can be classified Internal Organization of Processor Interconnection structure between processors Flow of information through system
- 5. M.J. Flynnclassify the computer on the basis ofnumber of instruction and data items processedsimultaneously. Single Instruction Stream, Single Data Stream(SISD) Single Instruction Stream, Multiple Data Stream(SIMD) Multiple Instruction Stream, Single Data Stream(MISD) Multiple Instruction Stream, Multiple Data Stream(MIMD)
- 6. SISD representsthe organization containing singlecontrol unit, a processor unit and a memory unit.Instruction are executed sequentially and systemmay or may not have internal parallel processingcapabilities. SIMD represents an organization that includes manyprocessing units under the supervision of a commoncontrol unit.
- 7. MISD structureis of only theoretical interest sinceno practical system has been constructed using thisorganization. MIMD organization refers to a computer systemcapable of processing several programs at the sametime.
- 8. Flynn’s classificationemphasize on the behavioralcharacteristics of the computer system rather thanits operational and structural interconnections. Onetype of parallel processing that does not fit in theFlynn’s classification is Pipelining. Parallel Processing can be discussed under followingtopics: Pipeline Processing Vector Processing Array Processors
- 9.Pipelining It isa technique of decomposing a sequential processinto sub operations, with each sub process beingexecuted in a special dedicated segments thatoperates concurrently with all other segments. Each segment performs partial processing dictatedby the way task is partitioned. The result obtained from each segment is transferredto next segment. The final result is obtained when data have passedthrough all segments.
- 10.Example Suppose wehave to perform the following task: Each sub operation is to be performed in a segmentwithin a pipeline. Each segment has one or tworegisters and a combinational circuit.
- 11. The suboperations in each segment of the pipelineare as follows:
- 14.General Consideration Letus consider the case where k segments pipelinewith a clock cycle time tp is used to execute n tasks. The first task T1 require time ktp to complete sincethere are k segments. The remaining (n-1) tasks emerge from pipe at therate one task per cycle. They will complete after time(n-1)tp. So total time required is k+(n-1) clock cycles. Calculate total cycles in previous example.
- 15. Now considernon pipeline unit that performs thesame operation and takes time equal to tn tocomplete each task. Total time required is ntn. The speedup ration is given as:
- 17.Arithmetic Pipeline Pipelinearithmetic units are usually found in veryhigh speed computers. They are used to implement floating pointoperations. We will now discuss the pipeline unit for the floatingpoint addition and subtraction.
- 18. The inputsto floating point adder pipeline are twonormalized floating point numbers. A and B are mantissas and a and b are theexponents. The floating point addition and subtraction can beperformed in four segments.
- 19. The sub-operationperformed in each segments are: Compare the exponents Align the mantissas Add or subtract the mantissas Normalize the result
- 21.Instruction Pipeline Pipelineprocessing can occur not only in the datastream but in the instruction stream as well. An instruction pipeline reads consecutive instructionfrom memory while previous instruction are beingexecuted in other segments. This caused the instruction fetch and executesegments to overlap and perform simultaneousoperation.
- 22.Four Segment CPUPipeline FI segment fetches the instruction. DA segment decodes the instruction and calculatethe effective address. FO segment fetches the operand. EX segment executes the instruction.
- 26.Handling Data DependencyThis problem can be solved in the following ways: Hardware interlocks: It is the circuit that detects theconflict situation and delayed the instruction by sufficientcycles to resolve the conflict. Operand Forwarding: It uses the special hardware todetect the conflict and avoid it by routing the datathrough the special path between pipeline segments. Delayed Loads: The compiler detects the data conflict andreorder the instruction as necessary to delay the loadingof the conflicting data by inserting no operationinstruction.
- 27.Handling of BranchInstruction Pre fetch the target instruction. Branch target buffer(BTB) included in the fetchsegment of the pipeline Branch Prediction Delayed Branch
- 28.RISC Pipeline Simplicityof instruction set is utilized to implementan instruction pipeline using small number of sub-operation, with each being executed in single clockcycle. Since all operation are performed in the register,there is no need of effective address calculation.
- 29.Three Segment InstructionPipeline I: Instruction Fetch A: ALU Operation E: Execute Instruction
- 30.
- 33.Delayed Branch Letus consider the program having the following 5instructions
- 36.Vector Processing Thereis a class of computational problems that arebeyond the capabilities of the conventionalcomputer. These are characterized by the fact that they requirevast number of computation and it take aconventional computer days or even weeks tocomplete. Computers with vector processing are able to handlesuch instruction and they have application infollowing fields:
- 37. Long rangeweather forecasting Petroleum exploration Seismic data analysis Medical diagnosis Aerodynamics and space simulation Artificial Intelligence and expert system Mapping the human genome Image Processing
- 38.Vector Operation Avector V of length n is represented as row vector by The element Vi of vector V is written as V(I) and theindex I refers to a memory address or register wherethe number is stored.
- 39. Let usconsider the program in assembly languagethat two vectors A and B of length 100 and put theresult in vector C.
- 40. A computercapable of vector processing eliminatesthe overhead associated with the time it takes tofetch and execute the instructions in the programloop. It allows operations to be specified with a singlevector instruction of the form:
- 42.Matrix Multiplication Letus consider the multiplication of two 3*3 matrixA and B.
- 43. This requiresthree multiplication and(afterinitializing c11 to 0) three addition. Total number of addition or multiplication requiredis 3*9. In general inner product consists of the sum of kproduct terms of the form:
- 44. In typicalapplication value of k may be 100 or even1000. The inner product calculation on a pipeline vectorprocessor is shown below. Floating point adder and multiplier are assumed tohave four segments each.
- 46. The fourpartial sum are added to form the final sum
- 47.
- 48.Array Processor Anarray processor is a processor that performs thecomputations on large arrays of data. There are two different types of array processor: Attached Array Processor SIMD Array Processor
- 49.Attached Array ProcessorIt is designed as a peripheral for a conventional hostcomputer. Its purpose is to enhance the performance of thecomputer by providing vector processing. It achieves high performance by means of parallelprocessing with multiple functional units.
- 51.SIMD Array ProcessorIt is processor which consists of multiple processingunit operating in parallel. The processing units are synchronized to performthe same task under control of common control unit. Each processor elements(PE) includes an ALU , afloating point arithmetic unit and working register.