Downloaded 1,581 times
![CS211 17Pipeline Performance: Speedup & Efficiencyk-stage pipeline processes n tasks in k + (n-1) clockcycles:k cycles for the first task and n-1 cyclesfor the remaining n-1 tasksTotal time to process n tasksTk = [ k + (n-1)] For the non-pipelined processorT1 = n k Speedup factorSk =T1Tk=n k [ k + (n-1)] =n kk + (n-1)7](/image.pl?url=https%3a%2f%2fimage.slidesharecdn.com%2fcaopresentationpipelining-161213185856%2f75%2fInstruction-pipeline-Computer-Architecture-17-2048.jpg&f=jpg&w=240)
Uploaded byInteX Research Lab
PPTX, PDF63,587 views
Instruction pipeline: Computer Architecture
Pipelining is a technique that allows multiple instructions to be executed in overlapping stages, improving efficiency, similar to processing laundry in stages. Each instruction undergoes fetching, decoding, executing, and memory operations in a structured pipeline, which can lead to significant time savings compared to non-pipelined execution. However, there are potential hazards such as structural, data, and control hazards that must be managed to maintain performance.
Recommended
More Related Content
What's hot
Similar to Instruction pipeline: Computer Architecture
More from InteX Research Lab
Recently uploaded
In this document
Powered by AI
Overview of pipelining as a series of stages where work is done in parallel, forming a pipeline for instruction processing.
Examines laundry processing as a case for understanding pipelining efficiency compared to non-pipelining, highlighting time benefits.
Defines pipelining as a speed-up technique for overlapping instruction execution on processors.
Details the steps involved in instruction execution within processors and how these steps can be pipelined for efficiency.
Describes six stages of instruction pipeline: Fetch, Decode, Calculate, Fetch Operands, Execute, and Write Operands.
Visual representation of the six-stage instruction pipelining concept.
Explains the clock cycle, latch delay, and frequency of the pipeline related to timing and performance.
Describes speedup and efficiency of k-stage pipelines processing n tasks, calculating total processing time.
Highlights benefits of pipelining and discusses potential hazards such as structural, data, and control hazards.
Final remarks and thank you, inviting any questions or further discussion.
Instruction pipeline: Computer Architecture
- 1.
- 2.• A Pipeliningis a series of stages, where some work is done ateach stage in parallel.• The stages are connected one to the next to form a pipe -instructions enter at one end, progress through the stages, and exitat the other end.
- 3.Pipelining Case: Laundry•4 loads of laundry that need to washed, dried, andfolded.– 30 minutes to wash, 40 min. to dry, and 20 min. to fold.– We have 1 washer, 1 dryer, and 1 folding station.• What’s the most efficient way to get the 4 loadsof laundry done?
- 4.Non Pipelined Laundry•Takes a total of 6 hours; nothing is done in parallel
- 5.Pipelined Laundry• Usingthis method, the laundry would be done at 9:30.
- 6.Definition:Pipelining is anspeed up technique where multipleinstructions are overlapped in execution on a processor.
- 7.Pipelining: Processors• Computers,like laundry, typically perform the exact samesteps for every instruction:– Fetch an instruction from memory– Decode the instruction– Execute the instruction– Read memory to get input– Write the result back to memory
- 8.CS211 8Instruction Pipeline•Instruction execution process lends itself naturally topipelining– overlap the subtasks of instruction fetch, decode and execute Fetch instruction (FI) Decode instruction (DI) Calculate operands (CO) Fetch operands (FO) Execute instructions (EI) Write result (WR)Overlap these operations• Instruction pipeline has six operations,
- 9.CS211 9Instructions Fetch•The IF stage is responsible for obtaining the requestedinstruction from memory. The instruction and the programcounter are stored in the register as temporary storage.
- 10.CS211 10Decode Instruction•The DI stage is responsible for decoding the instructionand sending out the various control lines to the otherparts of the processor.
- 11.CS211 11Calculate Operands•The CO stage is where any calculations are performed.The main component in this stage is the ALU. The ALUis made up of arithmetic, logic and capabilities.
- 12.CS211 12Fetch Operandsand Execute Instruction• The FO and EI stages are responsible for storing andloading values to and from memory. They also responsiblefor input and output from the processor respectively.
- 13.CS211 13Write Operands•The WO stage is responsible for writing the result of acalculation, memory access or input into the register file.
- 14.
- 15.Timing Diagram forInstructionPipeline Operation
- 16.CS211 16Pipeline Performance:Clock & TimingSi Si+1 m dClock cycle of the pipeline : Latch delay : d = max {m } + dPipeline frequency : ff = 1 / 6
- 17.CS211 17Pipeline Performance:Speedup & Efficiencyk-stage pipeline processes n tasks in k + (n-1) clockcycles:k cycles for the first task and n-1 cyclesfor the remaining n-1 tasksTotal time to process n tasksTk = [ k + (n-1)] For the non-pipelined processorT1 = n k Speedup factorSk =T1Tk=n k [ k + (n-1)] =n kk + (n-1)7
- 18.Advantages• Pipelining makesefficient use of resources.• Quicker time of execution of large number ofinstructions• The parallelism is invisible to the programmer.
- 19.CSE431 L06 BasicMIPS Pipelining.19 Irwin, PSU, 2005 Yes: Pipeline Hazards structural hazards: attempt to use the same resource by twodifferent instructions at the same time data hazards: attempt to use data before it is ready- An instruction’s source operand(s) are produced by a priorinstruction still in the pipeline control hazards: attempt to make a decision about programcontrol flow before the condition has been evaluated and thenew PC target address calculated- branch instructions Can always resolve hazards by waiting pipeline control must detect the hazard and take action to resolve hazardsCan Pipelining Get Us Into Trouble?
- 20.
- 21.Thank You!!!Md. SaidurRahman KohinoorE-mail: mdsaidur.r.kohinoor@ieee.orgFacebook: www.fb.com/kohinoor11