🔧 Digital Verification Engineers, Are You Ready for a Change? 🔧If you've been clocking in and out like a synchronous counter 🕒 but craving more excitement, I’ve got the reset button you need! 🔁 Whether you’re into RTL, UVM, or just good ol' debugging, there’s a spot waiting for your unique talents! 🌟Let’s find a place where your skills can oscillate at their full potential. 💡💼 Drop me a message, and let’s design your next career move together! 🚀#DigitalVerification #CareerGoals #EngineerOpportunities

To my friends in India who are asking where they can get a copy of “Next Level Testbenches: Design Patterns in SystemVerilog and UVM:”My understanding is that KDP (Kindle Direct Publishing, the publishing arm of Amazon) does not have a print on demand plant in India. Instead, Amazon India buys books from distributors in the US and the UK and resells them in India. However, they only buy paperback books, not hardcover books. So, I put together a paperback edition with identical content as the hardcover edition. The paperback edition launched this week on Amazon with “extended distribution,” which gives permission to be sold through international distributors. I don’t know when it will reach the Indian market. The KDP website says it could take up to eight weeks to get through the distribution network. In the meantime, it’s available on amazon.com, amazon.uk, and other European markets.I’m still learning how the international publishing market works. Thank you for your patience.P.S. Ebooks were not in my original plans. There are some challenges converting a book formatted for print into an ebook. I’ll look into it, but cannot promise an ebook edition will be available.

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I can share my experience based in India. As per my understanding :1: There will be high demand for VLSI background students or working professionals in the next five years due to semiconductor initiative.2: Once Indian semiconductor companies start manufacturing devices . There will be increased demand for embedded system background folks in validation.3: Semiconductor devices will be used for building embedded system platforms. It will increase the demand of hardware designers and firmware developers.4: For each silicon device there will be multiple hardware platforms. For each hardware platform, there will be multiple embedded application software opportunities. So demand for embedded application software folks will always increase.5: Will AI impact embedded software jobs ? I think it will help embedded software folks. Code generating tools exist for more than a decade and that didn't impact embedded software developers.Answer to Will firmware and embedded system hardware engineers be in higher demand than application software engineers? by Sanjay Kumar https://lnkd.in/gNbkCTCs#embedded #embedkari #opentowork

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On Day 45 of my 100 Days of RTL Coding, I focused on converting an SR flip-flop into a T flip-flop using Verilog. This conversion required reconfiguring the logic to achieve the toggling functionality of the T flip-flop while ensuring the Set and Reset inputs were appropriately utilized. Through this process, I deepened my understanding of flip-flop functionality and the relationships between different types of sequential circuits.Looking forward to more challenges and learning ahead!#RTL #Verilog #DigitalDesign #FlipFlop #100DaysOfRTL #Day45Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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How to start focussing and preparing for Semiconductor and AI from 2nd year of Engineering in ECE / EEE / CSE:[1] Mathematics:Not only essential for ML and VLSI but helps in Quantum Computing as well.Key concepts:a. Probability and Statistics - Bayes theorem, variance, standard deviation, Distributions, Regression, Bias, etc.b. Linear Algebra - Eigen values, Eigen vectors, Matrix operations.c. Complex Number - Complex Plane, Polar and exponential form, Fourier transform, Euler and De Moivre's theorem, Conjugate.[2] Digital Electronics:The most basic and fundamental subject for VLSI.Key Concepts:Boolean Algebra, Combinational and Sequential Circuit, FSM, Static Timing Analysis.Not covering in depth since already covered in earlier posts.[3] Analog Fundamentals:Key concepts:a.BJT, MOSFET, CMOS, Problems on CC, CE, CB, CS, CG and CD.b. Current Mirror, Amplifier, Oscillator, Implementing stick diagrams of basic gates and custom circuits, Drain calculation, triode and saturation region.[4] Algorithms:This subject is not essential and mandatory but when I look back i personally feel that this subject is a necessity to increase the intuitive thinking and problem solving approach.Key concepts:a. Divide and Conquer, Greedy, Dynamic Programming, Sorting and Searching, travelling Salesman, Dijkstra's, kruskal, etc.b. Complexity theory - P, NP, NP Hard and NP Complete.[5] HDL Coding:Verilog - Coding guidelines, Syntax and Semantics, Coding structure.The best way to learn is to start implementing the digital blocks like multiplexer, flip flops, basic gates, counters. If you don't have any tool use edaplayground.[6] Python:Libraries: Pytorch, pyuvm, NumPy, SciPy, scikit-learn.[7] Machine Learning:Key concepts:a. Supervised, Unsupervised, Reinforcement, Neural Networks, Gradient Descent, Deep learning, Back propagation.b. Frameworks like TPU and PyTorch.[8] SystemVerilog:a. Data types, Interface, Clocking Blocks, Modport, Virtual interface, Synthesizable and Non Synthesizable construct, Testbench infrastructure.[9] Protocols:AHB, APB, FIFO to start with.Interconnect the two domains of VLSI and AI by leveraging ML for Automation in Semiconductor and debug the Chip faster.#vlsi #asic #electricalengineering #electronics

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I come across multiple folks every year who want to switch job profile. It becomes difficult to switch after 2 years if person is not ready to relocate and compromise with salary. This is one of the reasons I recommend students to try embedded software career path first. I have conducted several surveys in LinkedIn for awareness purpose. Learning firmware or embedded software will definitely add value to PCB design background folks. Experienced folks can explore management role after firmware development skills. We have many hardware background folks in our Developer kit community. They got better opportunities after learning firmware programming. Our Ultra kit (Six months live session) can definitely help such folks due to several features: a: Learn C in various levels starting from Level 1. It depends on various types of C used in embedded software development. It includes logic building and project based hands-on approach. We have enough testimonials of C skills improvement in both students and working professionals.b: With longer duration, we can provide learning material for various architectures, RTOS, Linux and testing as well. c: PCB design background folks can try to design complete product. We have provision for this as well based on my past experience.Answer :This is possible but the complete switch over to embedded software will take some time. There are several factors :1: If you are from an ECE background, you might have studied Microprocessor and Digital Electronics. If not, you have to study these two first.2: You have to work on your C skills and learn firmware development with ARM based MCU.3: If your current CTC is above 14 LPA , you have to first try to find firmware development in your organization.4: You may also explore the team lead kind of role where you get some opportunity to work in firmware development..5: RTOS and Linux Application development can add value to your profile.6: You have to be flexible for relocation.7: Learning firmware development will definitely add value to your profile even if you don't get an immediate opportunity to switch.Answer to I have been working as PCB's design engineer for the past 7 years. I would like to switch over to the embedded software field. Is it possible? by Sanjay Kumar https://lnkd.in/gWtyirVq#embedded #opentowork #pcbdesign #embedkari

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Qualcomm vs ArmQualcomm's central processors are properly licensed under an agreement with Arm Holdings jury found.Arm's (O9Ty.F), shares were down 1.8% in extended trading after the news, and Qualcomm's (QCOM.O), shares were up 1.8%#Qualcomm #Arm #chip #licence #Nuvia

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🚨 Calling all Graduates!NVIDIA released its New Grad ASIC Verification Engineer role.Here's what you need to know:⚙ Located in Santa Clara, CA⚙ Full-time pay is ~$92,000-$180,000/yr⚙ Full-time(40hrs/week)So if you have And have experience in SystemVerilog, C and/or C++, Python and/or PerlThen consider applying to NVIDIA now!Here's the link 👇https://lnkd.in/gK7MNtDWYou got this!＿＿Found this useful? Consider re-sharing 🔁 and following me Mark Benliyan for more content like this!#newgrad #nvidia #coding #softwareengineering

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From Light Switches to Laptops: How logic Gates Define the World of Digital VLSI Design?🚀 Imagine tiny switches that can be turned on or off with electricity. These are basically logic gates, the building blocks of digital circuits. They take electrical signals as inputs (like a light switch being flipped on or off), perform a simple logical operation on those signals, and then output a new signal based on that operation.🚀 Logic gates perform basic operations like AND, OR, and NOT:AND Gate: The output is on (1) ONLY if ALL inputs are on (1).OR Gate: The output is on (1) if ANY input is on (1).NOT Gate: The output is the inverse of the input, flipping the signal (if the input is 1, the output is 0, and vice versa).By combining these simple operations in different ways, you can create complex digital circuits for all sorts of functions in a computer or device.🚀 Light switch: Imagine a simple light controlled by two switches. You want the light to be on only if BOTH switches are flipped on (think of a hallway light needing two switches at either end). This can be achieved with an AND gate. One input comes from each switch, and the output from the AND gate goes to the light bulb. Only when both inputs (switches) are on (flipped) will the output (light) turn on.🚀 Security system: Let's say you have a security system with a motion sensor and a door sensor. You want an alarm to sound if EITHER the motion sensor detects movement OR the door is opened. This can be built with an OR gate. One input comes from the motion sensor and the other from the door sensor. If EITHER input (sensor) detects something (goes on), the output from the OR gate will trigger the alarm.🚀 Traffic light controller: This one requires a combination of gates. We can use an AND gate to ensure both the pedestrian button is pressed AND there are no cars detected to allow pedestrian crossing. Similarly, we can use an OR gate to ensure EITHER a timer runs out OR a car is detected to switch the light to green for traffic.🚀 Basic arithmetic: Logic gates can even be used for simple math. By combining AND, OR, and NOT gates in specific ways, you can create circuits that perform operations like addition or subtraction on binary numbers (0s and 1s). These are the building blocks for more complex arithmetic units in computers.A detailed post is in comments. For all semiconductor and AI related content, follow TechoVedas

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Today's milestone is the design of a Synchronous FIFO (First In, First Out) using Verilog. A synchronous FIFO is a key component in digital systems, acting as a buffer to store and transfer data between components operating on the same clock domain.This implementation includes robust handling of read and write pointers, full and empty flags, and precise control over data flow. It ensures smooth and efficient data management, crucial for applications like communication protocols, data streaming, and pipelines.Each project sharpens my Verilog skills and understanding of RTL design. Progressing steadily toward the 100-day goal!#RTL #Verilog #FIFO #SynchronousFIFO #DigitalDesign #100DaysOfRTL #Day83Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis.By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Hello Linkedin Fam,Rivos Inc. India (Bengaluru) is looking to hire experienced professionals in #Ethernet #PCIe #PCIExpress #PCI #Accelerator #Fabric #CPU #FloatingPoint #Debug #Trace #Cache #DDR #DFI #MemoryController #DesignVerification #DV. If this is something which interests you; please ping with updated resumes. #3+ years ~ 14 yearsApart from Design Verification; there are vacancies for experienced professionals in #PhysicalDesign #CPU #SOC #PDV #PhysicalVerification #EMIR #SRAM #MemoryDesign #DFT #DesignForTest #Emulation #AcceleratorVerification #NOC Please like, share and help pass on the information to reach wider audience. Thank you all :) 😊 #jobopening #techjobs #engineeringcareers #RISC-V #accelerator #software #firmware #server #startuphiring

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification.Below are the key concepts which are needed to understand AXI protocol in depth.[1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI.[2] What are out of order and outstanding transaction in AXI.[3] What is the address boundary that slave can access in AXI.[4] Transfer mechanism for Write / Read with / without delay.[5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it.[6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type.[7] Difference b/w Bufferable and Cacheable type of transaction in AXI.[8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response.[9] What is a Locked access in AXI3. Why it is removed in AXI4.[10] What are the conditions for SLVERR and DECERR.[11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4.[12] Difference b/w AXI3 and AXI4.[13] What is a write interleaving method in AXI3 and why it's removed in AXI4.#vlsi #asic #semiconductorindustry #electricalengineering

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Hey folks!During my time at IIT Kanpur, many people asked me about analog design simulations, often wondering if there were any efficient, open-source tools available to create real-world designs. Well, the wait is over!I’m excited to introduce Xschem and Ngspice, two powerful tools for analog IC design. In this video, I walk you through the Xschem installation on a Linux machine.But that’s just the beginning! Up next, I’ll cover Ngspice, Open PDK, and Magic VLSI tool installation. After that, I’m launching a series on analog IC design — starting from basic simulations to designing real circuits.Stay connected, subscribe to my channel, and don’t forget to hit the bell icon for updates! Also, please share with all your fellow analog enthusiasts.#AnalogDesign #Xschem #Ngspice #VLSI #ICDesign #OpenSourceEDA #ElectronicsEngineering #SimulationTutorials #TechCommunity #LinuxTools

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Dear Chip Designers,...In the fast faced Semiconductor Industry, A Strong Individuals can Resolve Perceived Weaknesses in Teams. A New hire team lead can make or break the entire team, I have seen this multiple times. In the dynamic landscape of the Semiconductor industry, success often hinges on the collective strength of teams. However, even the most skilled teams may face challenges when dealing with perceived weaknesses among members.In this, lets delve into the transformative power of strong individuals in resolving these issues, ultimately fostering a culture of collaboration, innovation, and success.Identifying Perceived Weaknesses:Before delving into solutions, it's crucial to identify the perceived weaknesses that may hinder team performance. These can range from lack of technical proficiency to communication barriers or even interpersonal conflicts.The Role of Strong Individuals:Strong individuals possess a unique set of qualities that can significantly impact team dynamics.These individuals are not only technically proficient but also exhibit strong leadership, communication, and problem-solving skills. Their presence within teams can serve as a catalyst for positive change, bridging gaps and inspiring others to elevate their performance.Key Solutions and Strategies:Lead by Example: Strong individuals lead not only through their words but also through their actions. By setting high standards and demonstrating commitment to excellence, they inspire others to follow suit.Facilitate Open Communication: Effective communication is the cornerstone of successful teams.Strong individuals actively foster an environment where team members feel comfortable expressing their ideas, concerns, and feedback.Offer Mentorship and Support: Strong individuals recognize the importance of nurturing talent within the team. They willingly share their knowledge and experiences, empowering others to grow and develop their skills.Address Conflict Constructively: Conflict is inevitable within any team, but strong individuals approach it as an opportunity for growth rather than a hindrance.They facilitate constructive discussions and work towards finding mutually beneficial solutions.Celebrate Diversity: Strong individuals appreciate the value of diversity in perspectives and backgrounds. They actively seek out input from all team members, recognizing that innovation thrives in an inclusive environment.Case Studies and Success Stories:To illustrate the effectiveness of leveraging strong individuals within teams, we present real-life case studies from leading semiconductor companies.These stories highlight how the presence of strong individuals has transformed teams, overcoming challenges and achieving remarkable results.As we move forward, let us recognize and empower these individuals to drive positive change and propel our industry towards new heights.#semiconductor #Semiconductors #Chip #VLSI

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Basic and Simple Blueprint to structure a project in UVM [Important for VLSI Professionals]UVM is a preferred verification language due to its reusability, scalability, interoperability, CRV, proper phasing, etc.Below are the most simplest basic steps mentioned as how to develop a TB infrastructure from scratch.Step 1: Documentation✓ Go through the specification thoroughly and prepare the Verification Plan, Test Plan, Assertion Plan and understand the working of the IP or protocol.Step 2: Coding✓ Code the interface by listing all the I/O port. Code the Clocking block to avoid race condition, synchronization and direction to TB. Optionally code the Modport.***Note: Cautiously use the input / output skew and the clockvarThere are certain rules while using the Clocking block and modport which someone needs to follow.****✓ Code the transaction class and use the randomization wherever applicable. Try to avoid the field macros and instead use proper methods.**General thumb rule the input should be rand.Moreover try to use the do_copy, do_ compare, convert2string, do_print methods instead of using field macros which has a overhead**✓ Code the driver logic for the pin level activity at DUT. Use sequencer driver handshake properly depending on pipelined / non pipelined access.***Use proper coding guidelines while coding driver logic***✓ Code the Sequencer and use arbitration mechanism if needed.✓ Code the Monitor to handle the transaction. The analysis port first needs to be connected to Agent and then to other subscribers like scoreboards, etc.✓ Build the agent and give proper instantiation for Driver, monitor, and Sequencer. Depending on application the Agent can be chosen as either active or passive.✓ Code the env class and give proper connection.✓ Write some basic sequence items to check the flow along with base test class. While coding the sequence items number of methods can be used to execute the sequence.** While using the sequence use start_item/finish_item instead of `uvm_do macro **✓ Code the scoreboard either with the help of tlm fifo, associative array, queue depending on whether it's used in order or out of order comparator. The coding style will change depending on need.** While designing the Scoreboard make sure the predictor and evaluator are separate**There are almost 6 to 7 different methods of designing a scoreboard✓ Code the top module and use of run_test and set the config db.***Above are some of the very basic steps mentioned but ideally the testbench will be complex and use many more concepts which are not mentioned above. Some of them are:✓ Virtual Sequencer and Virtual Sequences.✓ RAL✓ Callbacks✓ Objection mechanism✓ Config and resource db✓ Coverage✓ Assertions#vlsi #asic #electronics #electricalengineering

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#fundamentalseries UVMMonitor Classes7. uvm_monitor * Observes DUT signals and converts them into transactions. * Sends transactions to other components like scoreboards and coverage collectors. * Passive component, does not drive signals.Environment Classes8. uvm_env * Container class for grouping related UVM components (e.g., agents, scoreboards). * Typically represents a complete verification environment for a specific DUT.Agent Classes9. uvm_agent * Groups related driver, sequencer, and monitor components. * Can be active (contains a driver and sequencer) or passive (contains only a monitor).Reporting Classes10. uvm_report_object * Provides reporting utilities for printing messages, warnings, and errors. * Base class for components that need reporting capabilities.11. uvm_report_server * Centralized reporting mechanism. * Collects and processes messages from uvm_report_object instances.Scoreboard and Analysis Classes12. uvm_scoreboard * Analyzes DUT outputs and compares them with expected results. * Receives transactions from monitors via analysis ports.13. uvm_analysis_port * Used for broadcasting transactions to one or more analysis components. * Example: uvm_analysis_port #(T)where T is the transaction type.14. uvm_analysis_imp * Implements the analysis export interface. * Used to connect analysis ports to scoreboards or other analysis components.#uvm #uvmmethodology #fundamentalseries #uvmconcepts #uvmsyntax #verification #testbenches #verificationengineer #training #mirafratechnologies

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How will AI impact and enable the semiconductor industry and what jobs exist in semiconductor industry ?Listen to this brief chat with Data &AI expert Lekhana Reddy on salaries and more..Where do you see AI impacting the semiconductor industry...would love to hear your thoughts below 👇🏾 https://lnkd.in/gb7rhvFH#semiconductorindustry #semiconductorsalaries #data hashtag#ai hashtag#genai

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UVM Based Test Bench Environment for Verification of APB ProtocolYet another project I had undertaken to enhance my skills in understanding and building effective UVM test bench environments from scratch. APB (Advanced Peripheral Bus) is part of the ARM AMBA (Advanced Microcontroller Bus Architecture) protocol family, designed for low-power, low-bandwidth communication with peripherals in a system-on-chip (SoC). APB is typically used for connecting to peripherals that do not require high-speed access, such as UARTs, timers, GPIOs, and other registers.About my project:1. Designed an APB RAM in SystemVerilog capable of storing and sending a total of 32 data elements each having a size of 32-bits2. Built UVM test bench components and the entire Verification Environment from scratch to verify functionality of APB protocol.3. Generated sequences for Write and Read operations in valid and invalid address ranges each having 15 transactions. Successfully verified functionality through behavioral simulation in Xilinx Vivado. Link for my project: https://lnkd.in/gVCkaNWF#rtldesign #rtlverification #vlsi #uvm #systemverilog #apb

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My Wishlist for EDA Tool Debugging Improvements 🛠️✨As someone who has worked across the VLSI spectrum—from architecture, design, and simulation to verification, formal methods, synthesis, STA, and physical design—I’ve noticed a significant gap in one critical area: debugging 🧐. While EDA tools have made strides in capacity and algorithmic improvements, debugging hasn’t kept up with user expectations.💡 Did you know? Studies show that most of the time of an engineer’s time is spent debugging. Think about the cost in terms of productivity and resources! Debugging inefficiencies don’t just waste time—they drain budgets 💸.Contrast this with modern mobile apps: when you click a button, complex calculations happen seamlessly in the background, delivering instant results. EDA tools? Not quite there yet.🚀 My Wishlist for Next-Level EDA Debugging1️⃣ Radical Improvements in Debugging Efficiency Incremental changes won’t cut it anymore. We need a 10X leap in debugging capabilities across the board. Time to disrupt the status quo! ⚡2️⃣ Seamless Collaboration Across Tools & Teams 🤝 Debugging should work across tools and teams:Start in an STA tool and seamlessly continue in a PD tool without losing context.Allow one engineer to pick up where another left off, enabling collaborative workflows.3️⃣ AI-Driven Triage & Root Cause Analysis 🤖 Let AI do the heavy lifting!Automatically triage regressions and link them to root causes.Use intelligent agents to save engineers from chasing issues manually, allowing more focus on innovation.Let’s rethink EDA debugging for the future 🌟. It’s time for tools to enable us, not hold us back. What’s on your debugging wishlist? Let’s connect and discuss!#EDA #VLSI #DebuggingRevolution #Innovation #TechWishList #Semiconductor #AI #ProductivityBoost #Engineering

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