1. General¶

• SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, aretracked per-thread.

• The presence of SVE is reported to userspace via HWCAP_SVE in the aux vectorAT_HWCAP entry. Presence of this flag implies the presence of the SVEinstructions and registers, and the Linux-specific system interfacesdescribed in this document. SVE is reported in /proc/cpuinfo as “sve”.

• Support for the execution of SVE instructions in userspace can also bedetected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRSinstruction, and checking that the value of the SVE field is nonzero. [3]

  It does not guarantee the presence of the system interfaces described in thefollowing sections: software that needs to verify that those interfaces arepresent must check for HWCAP_SVE instead.

• On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will alsobe reported in the AT_HWCAP2 aux vector entry. In addition to this,optional extensions to SVE2 may be reported by the presence of:

  HWCAP2_SVE2HWCAP2_SVEAESHWCAP2_SVEPMULLHWCAP2_SVEBITPERMHWCAP2_SVESHA3HWCAP2_SVESM4

  This list may be extended over time as the SVE architecture evolves.

  These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,which userspace can read using an MRS instruction. See elf_hwcaps.txt andcpu-feature-registers.txt for details.

• Debuggers should restrict themselves to interacting with the target via theNT_ARM_SVE regset. The recommended way of detecting support for this regsetis to connect to a target process first and then attempt aptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).

• Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memorybetween userspace and the kernel, the register value is encoded in memory inan endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded atbyte offset i from the start of the memory representation. This affects forexample the signal frame (struct sve_context) and ptrace interface(struct user_sve_header) and associated data.

  Beware that on big-endian systems this results in a different byte order thanfor the FPSIMD V-registers, which are stored as single host-endian 128-bitvalues, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded atbyte offset i. (struct fpsimd_context, struct user_fpsimd_state).

2. Vector length terminology¶

The size of an SVE vector (Z) register is referred to as the “vector length”.

To avoid confusion about the units used to express vector length, the kerneladopts the following conventions:

• Vector length (VL) = size of a Z-register in bytes
• Vector quadwords (VQ) = size of a Z-register in units of 128 bits

(So, VL = 16 * VQ.)

The VQ convention is used where the underlying granularity is important, suchas in data structure definitions. In most other situations, the VL conventionis used. This is consistent with the meaning of the “VL” pseudo-register inthe SVE instruction set architecture.

3. System call behaviour¶

• On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] ofZ0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFRbecome unspecified on return from a syscall.

• The SVE registers are not used to pass arguments to or receive results fromany syscall.

• In practice the affected registers/bits will be preserved or will be replacedwith zeros on return from a syscall, but userspace should not makeassumptions about this. The kernel behaviour may vary on a case-by-casebasis.

• All other SVE state of a thread, including the currently configured vectorlength, the state of the PR_SVE_VL_INHERIT flag, and the deferred vectorlength (if any), is preserved across all syscalls, subject to the specificexceptions for execve() described in section 6.

  In particular, on return from a fork() or clone(), the parent and new childprocess or thread share identical SVE configuration, matching that of theparent before the call.

4. Signal handling¶

• A new signal frame record sve_context encodes the SVE registers on signaldelivery. [1]
• This record is supplementary to fpsimd_context. The FPSR and FPCR registersare only present in fpsimd_context. For convenience, the content of V0..V31is duplicated between sve_context and fpsimd_context.
• The signal frame record for SVE always contains basic metadata, in particularthe thread’s vector length (in sve_context.vl).
• The SVE registers may or may not be included in the record, depending onwhether the registers are live for the thread. The registers are present ifand only if:sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
• If the registers are present, the remainder of the record has a vl-dependentsize and layout. Macros SVE_SIG_* are defined [1] to facilitate access tothe members.
• Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariantlayout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from thestart of the register’s representation in memory.
• If the SVE context is too big to fit in sigcontext.__reserved[], then extraspace is allocated on the stack, an extra_context record is written in__reserved[] referencing this space. sve_context is then written in theextra space. Refer to [1] for further details about this mechanism.

5. Signal return¶

When returning from a signal handler:

• If there is no sve_context record in the signal frame, or if the record ispresent but contains no register data as desribed in the previous section,then the SVE registers/bits become non-live and take unspecified values.
• If sve_context is present in the signal frame and contains full registerdata, the SVE registers become live and are populated with the specifieddata. However, for backward compatibility reasons, bits [127:0] of Z0..Z31are always restored from the corresponding members of fpsimd_context.vregs[]and not from sve_context. The remaining bits are restored from sve_context.
• Inclusion of fpsimd_context in the signal frame remains mandatory,irrespective of whether sve_context is present or not.
• The vector length cannot be changed via signal return. If sve_context.vl inthe signal frame does not match the current vector length, the signal returnattempt is treated as illegal, resulting in a forced SIGSEGV.

6. prctl extensions¶

Some new prctl() calls are added to allow programs to manage the SVE vectorlength:

prctl(PR_SVE_SET_VL, unsigned long arg)

Sets the vector length of the calling thread and related flags, wherearg == vl | flags. Other threads of the calling process are unaffected.

vl is the desired vector length, where sve_vl_valid(vl) must be true.

flags:

PR_SVE_VL_INHERIT

Inherit the current vector length across execve(). Otherwise, thevector length is reset to the system default at execve(). (SeeSection 9.)

PR_SVE_SET_VL_ONEXEC

Defer the requested vector length change until the next execve()performed by this thread.

The effect is equivalent to implicit exceution of the followingcall immediately after the next execve() (if any) by the thread:

prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)

This allows launching of a new program with a different vectorlength, while avoiding runtime side effects in the caller.

Without PR_SVE_SET_VL_ONEXEC, the requested change takes effectimmediately.

Return value: a nonnegative on success, or a negative value on error:

EINVAL: SVE not supported, invalid vector length requested, or

invalid flags.

On success:

• Either the calling thread’s vector length or the deferred vector lengthto be applied at the next execve() by the thread (dependent on whetherPR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest valuesupported by the system that is less than or equal to vl. If vl ==SVE_VL_MAX, the value set will be the largest value supported by thesystem.
• Any previously outstanding deferred vector length change in the callingthread is cancelled.
• The returned value describes the resulting configuration, encoded as forPR_SVE_GET_VL. The vector length reported in this value is the newcurrent vector length for this thread if PR_SVE_SET_VL_ONEXEC was notpresent in arg; otherwise, the reported vector length is the deferredvector length that will be applied at the next execve() by the callingthread.
• Changing the vector length causes all of P0..P15, FFR and all bits ofZ0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to becomeunspecified. Calling PR_SVE_SET_VL with vl equal to the thread’s currentvector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXECflag, does not constitute a change to the vector length for this purpose.

prctl(PR_SVE_GET_VL)

Gets the vector length of the calling thread.

The following flag may be OR-ed into the result:

PR_SVE_VL_INHERIT

Vector length will be inherited across execve().

There is no way to determine whether there is an outstanding deferredvector length change (which would only normally be the case between afork() or vfork() and the corresponding execve() in typical use).

To extract the vector length from the result, and it withPR_SVE_VL_LEN_MASK.

Return value: a nonnegative value on success, or a negative value on error:

EINVAL: SVE not supported.

7. ptrace extensions¶

• A new regset NT_ARM_SVE is defined for use with PTRACE_GETREGSET andPTRACE_SETREGSET.

  Refer to [2] for definitions.

The regset data starts with struct user_sve_header, containing:

size

Size of the complete regset, in bytes.This depends on vl and possibly on other things in the future.

If a call to PTRACE_GETREGSET requests less data than the value ofsize, the caller can allocate a larger buffer and retry in order toread the complete regset.

max_size

Maximum size in bytes that the regset can grow to for the targetthread. The regset won’t grow bigger than this even if the targetthread changes its vector length etc.

vl

Target thread’s current vector length, in bytes.

max_vl

Maximum possible vector length for the target thread.

flags

either

SVE_PT_REGS_FPSIMD

SVE registers are not live (GETREGSET) or are to be madenon-live (SETREGSET).

The payload is of type struct user_fpsimd_state, with the samemeaning as for NT_PRFPREG, starting at offsetSVE_PT_FPSIMD_OFFSET from the start of user_sve_header.

Extra data might be appended in the future: the size of thepayload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).

vq should be obtained using sve_vq_from_vl(vl).

or

SVE_PT_REGS_SVE

SVE registers are live (GETREGSET) or are to be made live(SETREGSET).

The payload contains the SVE register data, starting at offsetSVE_PT_SVE_OFFSET from the start of user_sve_header, and withsize SVE_PT_SVE_SIZE(vq, flags);

… OR-ed with zero or more of the following flags, which have the samemeaning and behaviour as the corresponding PR_SET_VL_* flags:

SVE_PT_VL_INHERIT

SVE_PT_VL_ONEXEC (SETREGSET only).

• The effects of changing the vector length and/or flags are equivalent tothose documented for PR_SVE_SET_VL.

  The caller must make a further GETREGSET call if it needs to know what VL isactually set by SETREGSET, unless is it known in advance that the requestedVL is supported.

• In the SVE_PT_REGS_SVE case, the size and layout of the payload depends onthe header fields. The SVE_PT_SVE_*() macros are provided to facilitateaccess to the members.

• In either case, for SETREGSET it is permissible to omit the payload, in whichcase only the vector length and flags are changed (along with anyconsequences of those changes).

• For SETREGSET, if an SVE_PT_REGS_SVE payload is present and therequested VL is not supported, the effect will be the same as if thepayload were omitted, except that an EIO error is reported. Noattempt is made to translate the payload data to the correct layoutfor the vector length actually set. The thread’s FPSIMD state ispreserved, but the remaining bits of the SVE registers becomeunspecified. It is up to the caller to translate the payload layoutfor the actual VL and retry.

• The effect of writing a partial, incomplete payload is unspecified.

8. ELF coredump extensions¶

• A NT_ARM_SVE note will be added to each coredump for each thread of thedumped process. The contents will be equivalent to the data that would havebeen read if a PTRACE_GETREGSET of NT_ARM_SVE were executed for each threadwhen the coredump was generated.

9. System runtime configuration¶

• To mitigate the ABI impact of expansion of the signal frame, a policymechanism is provided for administrators, distro maintainers and developersto set the default vector length for userspace processes:

/proc/sys/abi/sve_default_vector_length

Writing the text representation of an integer to this file sets the systemdefault vector length to the specified value, unless the value is greaterthan the maximum vector length supported by the system in which case thedefault vector length is set to that maximum.

The result can be determined by reopening the file and reading itscontents.

At boot, the default vector length is initially set to 64 or the maximumsupported vector length, whichever is smaller. This determines the initialvector length of the init process (PID 1).

Reading this file returns the current system default vector length.

• At every execve() call, the new vector length of the new process is set tothe system default vector length, unless

  • PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for thecalling thread, or
  • a deferred vector length change is pending, established via thePR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).

• Modifying the system default vector length does not affect the vector lengthof any existing process or thread that does not make an execve() call.

A.1. Registers¶

In A64 state, SVE adds the following:

• 32 8VL-bit vector registers Z0..Z31For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.

  A register write using a Vn register name zeros all bits of the correspondingZn except for bits [127:0].

• 16 VL-bit predicate registers P0..P15

• 1 VL-bit special-purpose predicate register FFR (the “first-fault register”)

• a VL “pseudo-register” that determines the size of each vector register

  The SVE instruction set architecture provides no way to write VL directly.Instead, it can be modified only by EL1 and above, by writing appropriatesystem registers.

• The value of VL can be configured at runtime by EL1 and above:16 <= VL <= VLmax, where VL must be a multiple of 16.

• The maximum vector length is determined by the hardware:16 <= VLmax <= 256.

  (The SVE architecture specifies 256, but permits future architecturerevisions to raise this limit.)

• FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-pointoperations in a similar way to the way in which they interact with ARMv8floating-point operations:

       8VL-1                       128               0  bit index    +----          ////            -----------------+ Z0 |                               :       V0      |  :                                          : Z7 |                               :       V7      | Z8 |                               :     * V8      |  :                                       :  :Z15 |                               :     *V15      |Z16 |                               :      V16      |  :                                          :Z31 |                               :      V31      |    +----          ////            -----------------+                                             31    0     VL-1                  0                +-------+    +----       ////      --+          FPSR |       | P0 |                       |               +-------+  : |                       |         *FPCR |       |P15 |                       |               +-------+    +----       ////      --+FFR |                       |               +-----+    +----       ////      --+            VL |     |                                            +-----+

(*) callee-save:

This only applies to bits [63:0] of Z-/V-registers.FPCR contains callee-save and caller-save bits. See [4] for details.

A.2. Procedure call standard¶

The ARMv8-A base procedure call standard is extended as follows with respect tothe additional SVE register state:

• All SVE register bits that are not shared with FP/SIMD are caller-save.

• Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.

  This follows from the way these bits are mapped to V8..V15, which are caller-save in the base procedure call standard.

      127           0  bit index     +---------------+  V0 |               |   : :               :  V7 |               |* V8 |               |:  : :               :*V15 |               | V16 |               |   : :               : V31 |               |     +---------------+              31    0             +-------+        FPSR |       |             +-------+       *FPCR |       |             +-------+