DSCR (Data Stream Control Register)¶

DSCR register in powerpc allows user to have some control of prefetch of datastream in the processor. Please refer to the ISA documents or related manualfor more detailed information regarding how to use this DSCR to attain thiscontrol of the prefetches . This document here provides an overview of kernelsupport for DSCR, related kernel objects, it’s functionalities and exporteduser interface.

1. Data Structures:

   1. thread_struct:

      dscr            /* Thread DSCR value */dscr_inherit    /* Thread has changed default DSCR */

   2. PACA:

      dscr_default    /* per-CPU DSCR default value */

   3. sysfs.c:

      dscr_default    /* System DSCR default value */

2. Scheduler Changes:

   Scheduler will write the per-CPU DSCR default which is stored in theCPU’s PACA value into the register if the thread has dscr_inherit valuecleared which means that it has not changed the default DSCR till now.If the dscr_inherit value is set which means that it has changed thedefault DSCR value, scheduler will write the changed value which willnow be contained in thread struct’s dscr into the register instead ofthe per-CPU default PACA based DSCR value.

   NOTE: Please note here that the system wide global DSCR value nevergets used directly in the scheduler process context switch at all.

3. SYSFS Interface:

   • Global DSCR default: /sys/devices/system/cpu/dscr_default
   • CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr

   Changing the global DSCR default in the sysfs will change all the CPUspecific DSCR defaults immediately in their PACA structures. Again ifthe current process has the dscr_inherit clear, it also writes the newvalue into every CPU’s DSCR register right away and updates the currentthread’s DSCR value as well.

   Changing the CPU specific DSCR default value in the sysfs does exactlythe same thing as above but unlike the global one above, it just changesstuff for that particular CPU instead for all the CPUs on the system.

4. User Space Instructions:

   The DSCR register can be accessed in the user space using any of thesetwo SPR numbers available for that purpose.

   1. Problem state SPR: 0x03 (Un-privileged, POWER8 only)
   2. Privileged state SPR: 0x11 (Privileged)

   Accessing DSCR through privileged SPR number (0x11) from user spaceworks, as it is emulated following an illegal instruction exceptioninside the kernel. Both mfspr and mtspr instructions are emulated.

   Accessing DSCR through user level SPR (0x03) from user space will firstcreate a facility unavailable exception. Inside this exception handlerall mfspr instruction based read attempts will get emulated and returnedwhere as the first mtspr instruction based write attempts will enablethe DSCR facility for the next time around (both for read and write) bysetting DSCR facility in the FSCR register.

5. Specifics about ‘dscr_inherit’:

   The thread struct element ‘dscr_inherit’ represents whether the threadin question has attempted and changed the DSCR itself using any of thefollowing methods. This element signifies whether the thread wants touse the CPU default DSCR value or its own changed DSCR value in thekernel.

   1. mtspr instruction (SPR number 0x03)
   2. mtspr instruction (SPR number 0x11)
   3. ptrace interface (Explicitly set user DSCR value)

   Any child of the process created after this event in the process inheritsthis same behaviour as well.