drm/amdgpu AMDgpu driver¶

The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics CoreNext (GCN) architecture.

Module Parameters¶

The amdgpu driver supports the following module parameters:

vramlimit (int)

Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).

vis_vramlimit (int)

Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).

gartsize (uint)

Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).

gttsize (int)

Restrict the size of GTT domain in MiB for testing. The default is -1 (It’s VRAM size if 3GB < VRAM < 3/4 RAM,otherwise 3/4 RAM size).

moverate (int)

Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).

benchmark (int)

Run benchmarks. The default is 0 (Skip benchmarks).

test (int)

Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).

audio (int)

Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.

disp_priority (int)

Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).

hw_i2c (int)

To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).

pcie_gen2 (int)

To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).

msi (int)

To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).

lockup_timeout (string)

Set GPU scheduler timeout value in ms.

The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one ormultiple values specified. 0 and negative values are invalidated. They will be adjustedto the default timeout.

With one value specified, the setting will apply to all non-compute jobs.
With multiple values specified, the first one will be for GFX.The second one is for Compute. The third and fourth ones arefor SDMA and Video.

By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)jobs is 10000. And there is no timeout enforced on compute jobs.

dpm (int)

Override for dynamic power management setting(0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)The default is -1 (auto).

fw_load_type (int)

Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).

aspm (int)

To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).

runpm (int)

Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power downthe dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.

ip_block_mask (uint)

Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not havesome IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output inthe kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).

bapm (int)

Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.The default -1 (auto, enabled)

deep_color (int)

Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).

vm_size (int)

Override the size of the GPU’s per client virtual address space in GiB. The default is -1 (automatic for each asic).

vm_fragment_size (int)

Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).

vm_block_size (int)

Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).

vm_fault_stop (int)

Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).

vm_debug (int)

Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).

vm_update_mode (int)

Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The defaultis -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).

exp_hw_support (int)

Enable experimental hw support (1 = enable). The default is 0 (disabled).

dc (int)

Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).

sched_jobs (int)

Override the max number of jobs supported in the sw queue. The default is 32.

sched_hw_submission (int)

Override the max number of HW submissions. The default is 2.

ppfeaturemask (uint)

Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.The default is the current set of stable power features.

forcelongtraining (uint)

Force long memory training in resume.The default is zero, indicates short training in resume.

pcie_gen_cap (uint)

Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.The default is 0 (automatic for each asic).

pcie_lane_cap (uint)

Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.The default is 0 (automatic for each asic).

cg_mask (uint)

Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags indrivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).

pg_mask (uint)

Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags indrivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).

sdma_phase_quantum (uint)

Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.

disable_cu (charp)

Set to disable CUs (It’s set like se.sh.cu,…). The default is NULL.

virtual_display (charp)

Set to enable virtual display feature. This feature provides a virtual display hardware on headless boardsor in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It’s the pci address ofthe device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pcidevice at 26:00.0. The default is NULL.

job_hang_limit (int)

Set how much time allow a job hang and not drop it. The default is 0.

lbpw (int)

Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).

gpu_recovery (int)

Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).

emu_mode (int)

Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).

ras_enable (int)

Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))

ras_mask (uint)

Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

si_support (int)

Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,otherwise using amdgpu driver.

cik_support (int)

Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,otherwise using amdgpu driver.

smu_memory_pool_size (uint)

It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).

async_gfx_ring (int)

It is used to enable gfx rings that could be configured with different prioritites or equal priorities

mcbp (int)

It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)

discovery (int)

Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.(-1 = auto (default), 0 = disabled, 1 = enabled)

mes (int)

Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.(0 = disabled (default), 1 = enabled)

force_asic_type (int)

A non negative value used to specify the asic type for all supported GPUs.

sched_policy (int)

Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.Setting 1 disables over-subscription. Setting 2 disables HWS and staticallyassigns queues to HQDs.

hws_max_conc_proc (int)

Maximum number of processes that HWS can schedule concurrently. The maximum is thenumber of VMIDs assigned to the HWS, which is also the default.

cwsr_enable (int)

CWSR(compute wave store and resume) allows the GPU to preempt shader execution inthe middle of a compute wave. Default is 1 to enable this feature. Setting 0disables it.

max_num_of_queues_per_device (int)

Maximum number of queues per device. Valid setting is between 1 and 4096. Defaultis 4096.

send_sigterm (int)

Send sigterm to HSA process on unhandled exceptions. Default is not to send sigtermbut just print errors on dmesg. Setting 1 enables sending sigterm.

debug_largebar (int)

Set debug_largebar as 1 to enable simulating large-bar capability on non-large barsystem. This limits the VRAM size reported to ROCm applications to the visiblesize, usually 256MB.Default value is 0, diabled.

ignore_crat (int)

Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRATtable to get information about AMD APUs. This option can serve as a workaround onsystems with a broken CRAT table.

halt_if_hws_hang (int)

Halt if HWS hang is detected. Default value, 0, disables the halt on hang.Setting 1 enables halt on hang.

hws_gws_support(bool)

Assume that HWS supports GWS barriers regardless of what firmware versioncheck says. Default value: false (rely on MEC2 firmware version check).

queue_preemption_timeout_ms (int)

queue preemption timeout in ms (1 = Minimum, 9000 = default)

debug_evictions(bool)

Enable extra debug messages to help determine the cause of evictions

dcfeaturemask (uint)

Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.The default is the current set of stable display features.

dcdebugmask (uint)

Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.

abmlevel (uint)

Override the default ABM (Adaptive Backlight Management) level used for DCenabled hardware. Requires DMCU to be supported and loaded.Valid levels are 0-4. A value of 0 indicates that ABM should be disabled bydefault. Values 1-4 control the maximum allowable brightness reduction viathe ABM algorithm, with 1 being the least reduction and 4 being the mostreduction.

Defaults to 0, or disabled. Userspace can still override this level laterafter boot.

tmz (int)

Trusted Memory Zone (TMZ) is a method to protect data being writtento or read from memory.

The default value: 0 (off). TODO: change to auto till it is completed.

reset_method (int)

GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

Core Driver Infrastructure¶

This section covers core driver infrastructure.

Memory Domains¶

AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.Memory in this pool could be swapped out to disk if there is pressure.

AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into theGPU’s virtual address space via gart. Gart memory linearizes non-contiguouspages of system memory, allows GPU access system memory in a linezrizedfashion.

AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memorycarved out by the BIOS.

AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share dataacross shader threads.

AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize theexecution of all the waves on a device.

AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute enginesfor appending data.

Buffer Objects¶

This defines the interfaces to operate on anamdgpu_bo buffer object whichrepresents memory used by driver (VRAM, system memory, etc.). The driverprovides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfacesto create/destroy/set buffer object which are then managed by the kernel TTMmemory manager.The interfaces are also used internally by kernel clients, including gfx,uvd, etc. for kernel managed allocations used by the GPU.

voidamdgpu_bo_subtract_pin_size(struct amdgpu_bo * bo)¶: Remove BO from pin_size accounting

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object

Description

This function is called when a BO stops being pinned, and updates theamdgpu_device pin_size values accordingly.

boolamdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object * bo)¶: check if the buffer object is anamdgpu_bo

Parameters

structttm_buffer_object*bo: buffer object to be checked

Description

Uses destroy function associated with the object to determine if this isanamdgpu_bo.

Return

true if the object belongs toamdgpu_bo, false if not.

voidamdgpu_bo_placement_from_domain(struct amdgpu_bo * abo, u32 domain)¶: set buffer’s placement

Parameters

structamdgpu_bo*abo: amdgpu_bo buffer object whose placement is to be set
u32domain: requested domain

Description

Sets buffer’s placement according to requested domain and the buffer’sflags.

intamdgpu_bo_create_reserved(struct amdgpu_device * adev, unsigned long size, int align, u32 domain, struct amdgpu_bo ** bo_ptr, u64 * gpu_addr, void ** cpu_addr)¶: create reserved BO for kernel use

Parameters

structamdgpu_device*adev: amdgpu device object
unsignedlongsize: size for the new BO
intalign: alignment for the new BO
u32domain: where to place it
structamdgpu_bo**bo_ptr: used to initialize BOs in structures
u64*gpu_addr: GPU addr of the pinned BO
void**cpu_addr: optional CPU address mapping

Description

Allocates and pins a BO for kernel internal use, and returns it stillreserved.

Note

For bo_ptr new BO is only created if bo_ptr points to NULL.

Return

0 on success, negative error code otherwise.

intamdgpu_bo_create_kernel(struct amdgpu_device * adev, unsigned long size, int align, u32 domain, struct amdgpu_bo ** bo_ptr, u64 * gpu_addr, void ** cpu_addr)¶: create BO for kernel use

Parameters

structamdgpu_device*adev: amdgpu device object
unsignedlongsize: size for the new BO
intalign: alignment for the new BO
u32domain: where to place it
structamdgpu_bo**bo_ptr: used to initialize BOs in structures
u64*gpu_addr: GPU addr of the pinned BO
void**cpu_addr: optional CPU address mapping

Description

Allocates and pins a BO for kernel internal use.

Note

For bo_ptr new BO is only created if bo_ptr points to NULL.

Return

0 on success, negative error code otherwise.

intamdgpu_bo_create_kernel_at(struct amdgpu_device * adev, uint64_t offset, uint64_t size, uint32_t domain, struct amdgpu_bo ** bo_ptr, void ** cpu_addr)¶: create BO for kernel use at specific location

Parameters

structamdgpu_device*adev: amdgpu device object
uint64_toffset: offset of the BO
uint64_tsize: size of the BO
uint32_tdomain: where to place it
structamdgpu_bo**bo_ptr: used to initialize BOs in structures
void**cpu_addr: optional CPU address mapping

Description

Creates a kernel BO at a specific offset in the address space of the domain.

Return

0 on success, negative error code otherwise.

voidamdgpu_bo_free_kernel(struct amdgpu_bo ** bo, u64 * gpu_addr, void ** cpu_addr)¶: free BO for kernel use

Parameters

structamdgpu_bo**bo: amdgpu BO to free
u64*gpu_addr: pointer to where the BO’s GPU memory space address was stored
void**cpu_addr: pointer to where the BO’s CPU memory space address was stored

Description

unmaps and unpin a BO for kernel internal use.

intamdgpu_bo_create(struct amdgpu_device * adev, struct amdgpu_bo_param * bp, struct amdgpu_bo ** bo_ptr)¶: create anamdgpu_bo buffer object

Parameters

structamdgpu_device*adev: amdgpu device object
structamdgpu_bo_param*bp: parameters to be used for the buffer object
structamdgpu_bo**bo_ptr: pointer to the buffer object pointer

Description

Creates anamdgpu_bo buffer object; and if requested, also creates ashadow object.Shadow object is used to backup the original buffer object, and is alwaysin GTT.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_validate(struct amdgpu_bo * bo)¶: validate anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: pointer to the buffer object

Description

Sets placement according to domain; and changes placement and cachingpolicy of the buffer object according to the placement.This is used for validating shadow bos. It calls ttm_bo_validate() tomake sure the buffer is resident where it needs to be.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_restore_shadow(struct amdgpu_bo * shadow, structdma_fence ** fence)¶: restore anamdgpu_bo shadow

Parameters

structamdgpu_bo*shadow: amdgpu_bo shadow to be restored
structdma_fence**fence: dma_fence associated with the operation

Description

Copies a buffer object’s shadow content back to the object.This is used for recovering a buffer from its shadow in case of a gpureset where vram context may be lost.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_kmap(struct amdgpu_bo * bo, void ** ptr)¶: map anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object to be mapped
void**ptr: kernel virtual address to be returned

Description

Calls ttm_bo_kmap() to set up the kernel virtual mapping; callsamdgpu_bo_kptr() to get the kernel virtual address.

Return

0 for success or a negative error code on failure.

void *amdgpu_bo_kptr(struct amdgpu_bo * bo)¶: returns a kernel virtual address of the buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object

Description

Calls ttm_kmap_obj_virtual() to get the kernel virtual address

Return

the virtual address of a buffer object area.

voidamdgpu_bo_kunmap(struct amdgpu_bo * bo)¶: unmap anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object to be unmapped

Description

Unmaps a kernel map set up byamdgpu_bo_kmap().

struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo * bo)¶: reference anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object

Description

References the containedttm_buffer_object.

Return

a refcounted pointer to theamdgpu_bo buffer object.

voidamdgpu_bo_unref(struct amdgpu_bo ** bo)¶: unreference anamdgpu_bo buffer object

Parameters

structamdgpu_bo**bo: amdgpu_bo buffer object

Description

Unreferences the containedttm_buffer_object and clear the pointer

intamdgpu_bo_pin_restricted(struct amdgpu_bo * bo, u32 domain, u64 min_offset, u64 max_offset)¶: pin anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object to be pinned
u32domain: domain to be pinned to
u64min_offset: the start of requested address range
u64max_offset: the end of requested address range

Description

Pins the buffer object according to requested domain and address range. Ifthe memory is unbound gart memory, binds the pages into gart table. Adjustspin_count and pin_size accordingly.

Pinning means to lock pages in memory along with keeping them at a fixedoffset. It is required when a buffer can not be moved, for example, whena display buffer is being scanned out.

Compared withamdgpu_bo_pin(), this function gives more flexibility onwhere to pin a buffer if there are specific restrictions on where a buffermust be located.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_pin(struct amdgpu_bo * bo, u32 domain)¶: pin anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object to be pinned
u32domain: domain to be pinned to

Description

A simple wrapper toamdgpu_bo_pin_restricted().Provides a simpler API for buffers that do not have any strict restrictionson where a buffer must be located.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_unpin(struct amdgpu_bo * bo)¶: unpin anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object to be unpinned

Description

Decreases the pin_count, and clears the flags if pin_count reaches 0.Changes placement and pin size accordingly.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_evict_vram(struct amdgpu_device * adev)¶: evict VRAM buffers

Parameters

structamdgpu_device*adev: amdgpu device object

Description

Evicts all VRAM buffers on the lru list of the memory type.Mainly used for evicting vram at suspend time.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_init(struct amdgpu_device * adev)¶: initialize memory manager

Parameters

structamdgpu_device*adev: amdgpu device object

Description

Calls amdgpu_ttm_init() to initialize amdgpu memory manager.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_late_init(struct amdgpu_device * adev)¶: late init

Parameters

structamdgpu_device*adev: amdgpu device object

Description

Calls amdgpu_ttm_late_init() to free resources used earlier duringinitialization.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_fini(struct amdgpu_device * adev)¶: tear down memory manager

Parameters

structamdgpu_device*adev: amdgpu device object

Description

Reversesamdgpu_bo_init() to tear down memory manager.

intamdgpu_bo_fbdev_mmap(struct amdgpu_bo * bo, struct vm_area_struct * vma)¶: mmap fbdev memory

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object
structvm_area_struct*vma: vma as input from the fbdev mmap method

Description

Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_set_tiling_flags(struct amdgpu_bo * bo, u64 tiling_flags)¶: set tiling flags

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object
u64tiling_flags: new flags

Description

Sets buffer object’s tiling flags with the new one. Used by GEM ioctl orkernel driver to set the tiling flags on a buffer.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_get_tiling_flags(struct amdgpu_bo * bo, u64 * tiling_flags)¶: get tiling flags

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object
u64*tiling_flags: returned flags

Description

Gets buffer object’s tiling flags. Used by GEM ioctl or kernel driver toset the tiling flags on a buffer.

intamdgpu_bo_set_metadata(struct amdgpu_bo * bo, void * metadata, uint32_t metadata_size, uint64_t flags)¶: set metadata

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object
void*metadata: new metadata
uint32_tmetadata_size: size of the new metadata
uint64_tflags: flags of the new metadata

Description

Sets buffer object’s metadata, its size and flags.Used via GEM ioctl.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_get_metadata(struct amdgpu_bo * bo, void * buffer, size_t buffer_size, uint32_t * metadata_size, uint64_t * flags)¶: get metadata

Parameters

structamdgpu_bo*bo: amdgpu_bo buffer object
void*buffer: returned metadata
size_tbuffer_size: size of the buffer
uint32_t*metadata_size: size of the returned metadata
uint64_t*flags: flags of the returned metadata

Description

Gets buffer object’s metadata, its size and flags. buffer_size shall not beless than metadata_size.Used via GEM ioctl.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_move_notify(struct ttm_buffer_object * bo, bool evict, struct ttm_mem_reg * new_mem)¶: notification about a memory move

Parameters

structttm_buffer_object*bo: pointer to a buffer object
boolevict: if this move is evicting the buffer from the graphics address space
structttm_mem_reg*new_mem: new information of the bufer object

Description

Marks the correspondingamdgpu_bo buffer object as invalid, also performsbookkeeping.TTM driver callback which is called when ttm moves a buffer.

voidamdgpu_bo_release_notify(struct ttm_buffer_object * bo)¶: notification about a BO being released

Parameters

structttm_buffer_object*bo: pointer to a buffer object

Description

Wipes VRAM buffers whose contents should not be leaked before thememory is released.

intamdgpu_bo_fault_reserve_notify(struct ttm_buffer_object * bo)¶: notification about a memory fault

Parameters

structttm_buffer_object*bo: pointer to a buffer object

Description

Notifies the driver we are taking a fault on this BO and have reserved it,also performs bookkeeping.TTM driver callback for dealing with vm faults.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_fence(struct amdgpu_bo * bo, structdma_fence * fence, bool shared)¶: add fence to buffer object

Parameters

structamdgpu_bo*bo: buffer object in question
structdma_fence*fence: fence to add
boolshared: true if fence should be added shared

intamdgpu_bo_sync_wait_resv(struct amdgpu_device * adev, structdma_resv * resv, enum amdgpu_sync_mode sync_mode, void * owner, bool intr)¶: Wait for BO reservation fences

Parameters

structamdgpu_device*adev: amdgpu device pointer
structdma_resv*resv: reservation object to sync to
enumamdgpu_sync_modesync_mode: synchronization mode
void*owner: fence owner
boolintr: Whether the wait is interruptible

Description

Extract the fences from the reservation object and waits for them to finish.

Return

0 on success, errno otherwise.

intamdgpu_bo_sync_wait(struct amdgpu_bo * bo, void * owner, bool intr)¶: Wrapper for amdgpu_bo_sync_wait_resv

Parameters

structamdgpu_bo*bo: buffer object to wait for
void*owner: fence owner
boolintr: Whether the wait is interruptible

Description

Wrapper to wait for fences in a BO.

Return

0 on success, errno otherwise.

u64amdgpu_bo_gpu_offset(struct amdgpu_bo * bo)¶: return GPU offset of bo

Parameters

structamdgpu_bo*bo: amdgpu object for which we query the offset

Note

object should either be pinned or reserved when calling thisfunction, it might be useful to add check for this for debugging.

Return

current GPU offset of the object.

u64amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo * bo)¶: return GPU offset of bo

Parameters

structamdgpu_bo*bo: amdgpu object for which we query the offset

Return

current GPU offset of the object without raising warnings.

uint32_tamdgpu_bo_get_preferred_pin_domain(struct amdgpu_device * adev, uint32_t domain)¶: get preferred domain for scanout

Parameters

structamdgpu_device*adev: amdgpu device object
uint32_tdomain: allowedmemory domains

Return

Which of the allowed domains is preferred for pinning the BO for scanout.

PRIME Buffer Sharing¶

The following callback implementations are used forsharing GEM bufferobjects between different devices via PRIME.

void *amdgpu_gem_prime_vmap(structdrm_gem_object * obj)¶: dma_buf_ops.vmap implementation

Parameters

structdrm_gem_object*obj: GEM BO

Description

Sets up an in-kernel virtual mapping of the BO’s memory.

Return

The virtual address of the mapping or an error pointer.

voidamdgpu_gem_prime_vunmap(structdrm_gem_object * obj, void * vaddr)¶: dma_buf_ops.vunmap implementation

Parameters

structdrm_gem_object*obj: GEM BO
void*vaddr: Virtual address (unused)

Description

Tears down the in-kernel virtual mapping of the BO’s memory.

intamdgpu_gem_prime_mmap(structdrm_gem_object * obj, struct vm_area_struct * vma)¶: drm_driver.gem_prime_mmap implementation

Parameters

structdrm_gem_object*obj: GEM BO
structvm_area_struct*vma: Virtual memory area

Description

Sets up a userspace mapping of the BO’s memory in the givenvirtual memory area.

Return

0 on success or a negative error code on failure.

intamdgpu_dma_buf_attach(structdma_buf * dmabuf, structdma_buf_attachment * attach)¶: dma_buf_ops.attach implementation

Parameters

structdma_buf*dmabuf: DMA-buf where we attach to
structdma_buf_attachment*attach: attachment to add

Description

Add the attachment as user to the exported DMA-buf.

voidamdgpu_dma_buf_detach(structdma_buf * dmabuf, structdma_buf_attachment * attach)¶: dma_buf_ops.detach implementation

Parameters

structdma_buf*dmabuf: DMA-buf where we remove the attachment from
structdma_buf_attachment*attach: the attachment to remove

Description

Called when an attachment is removed from the DMA-buf.

intamdgpu_dma_buf_pin(structdma_buf_attachment * attach)¶: dma_buf_ops.pin implementation

Parameters

structdma_buf_attachment*attach: attachment to pin down

Description

Pin the BO which is backing the DMA-buf so that it can’t move any more.

voidamdgpu_dma_buf_unpin(structdma_buf_attachment * attach)¶: dma_buf_ops.unpin implementation

Parameters

structdma_buf_attachment*attach: attachment to unpin

Description

Unpin a previously pinned BO to make it movable again.

struct sg_table *amdgpu_dma_buf_map(structdma_buf_attachment * attach, enum dma_data_direction dir)¶: dma_buf_ops.map_dma_buf implementation

Parameters

structdma_buf_attachment*attach: DMA-buf attachment
enumdma_data_directiondir: DMA direction

Description

Makes sure that the shared DMA buffer can be accessed by the target device.For now, simply pins it to the GTT domain, where it should be accessible byall DMA devices.

Return

sg_table filled with the DMA addresses to use or ERR_PRT with negative errorcode.

voidamdgpu_dma_buf_unmap(structdma_buf_attachment * attach, struct sg_table * sgt, enum dma_data_direction dir)¶: dma_buf_ops.unmap_dma_buf implementation

Parameters

structdma_buf_attachment*attach: DMA-buf attachment
structsg_table*sgt: sg_table to unmap
enumdma_data_directiondir: DMA direction

Description

This is called when a shared DMA buffer no longer needs to be accessible byanother device. For now, simply unpins the buffer from GTT.

intamdgpu_dma_buf_begin_cpu_access(structdma_buf * dma_buf, enum dma_data_direction direction)¶: dma_buf_ops.begin_cpu_access implementation

Parameters

structdma_buf*dma_buf: Shared DMA buffer
enumdma_data_directiondirection: Direction of DMA transfer

Description

This is called before CPU access to the shared DMA buffer’s memory. If it’sa read access, the buffer is moved to the GTT domain if possible, for optimalCPU read performance.

Return

0 on success or a negative error code on failure.

structdma_buf *amdgpu_gem_prime_export(structdrm_gem_object * gobj, int flags)¶: drm_driver.gem_prime_export implementation

Parameters

structdrm_gem_object*gobj: GEM BO
intflags: Flags such as DRM_CLOEXEC and DRM_RDWR.

Description

The main work is done by thedrm_gem_prime_export helper.

Return

Shared DMA buffer representing the GEM BO from the given device.

structdrm_gem_object *amdgpu_dma_buf_create_obj(structdrm_device * dev, structdma_buf * dma_buf)¶: create BO for DMA-buf import

Parameters

structdrm_device*dev: DRM device
structdma_buf*dma_buf: DMA-buf

Description

Creates an empty SG BO for DMA-buf import.

Return

A new GEM BO of the given DRM device, representing the memorydescribed by the given DMA-buf attachment and scatter/gather table.

voidamdgpu_dma_buf_move_notify(structdma_buf_attachment * attach)¶: attach.move_notify implementation

Parameters

structdma_buf_attachment*attach: the DMA-buf attachment

Description

Invalidate the DMA-buf attachment, making sure that the we re-create themapping before the next use.

structdrm_gem_object *amdgpu_gem_prime_import(structdrm_device * dev, structdma_buf * dma_buf)¶: drm_driver.gem_prime_import implementation

Parameters

structdrm_device*dev: DRM device
structdma_buf*dma_buf: Shared DMA buffer

Description

Import a dma_buf into a the driver and potentially create a new GEM object.

Return

GEM BO representing the shared DMA buffer for the given device.

MMU Notifier¶

For coherent userptr handling registers an MMU notifier to inform the driverabout updates on the page tables of a process.

When somebody tries to invalidate the page tables we block the update untilall operations on the pages in question are completed, then those pages aremarked as accessed and also dirty if it wasn’t a read only access.

New command submissions using the userptrs in question are delayed until allpage table invalidation are completed and we once more see a coherent processaddress space.

boolamdgpu_mn_invalidate_gfx(struct mmu_interval_notifier * mni, const struct mmu_notifier_range * range, unsigned long cur_seq)¶: callback to notify about mm change

Parameters

structmmu_interval_notifier*mni: the range (mm) is about to update
conststructmmu_notifier_range*range: details on the invalidation
unsignedlongcur_seq: Value to pass to mmu_interval_set_seq()

Description

Block for operations on BOs to finish and mark pages as accessed andpotentially dirty.

boolamdgpu_mn_invalidate_hsa(struct mmu_interval_notifier * mni, const struct mmu_notifier_range * range, unsigned long cur_seq)¶: callback to notify about mm change

Parameters

structmmu_interval_notifier*mni: the range (mm) is about to update
conststructmmu_notifier_range*range: details on the invalidation
unsignedlongcur_seq: Value to pass to mmu_interval_set_seq()

Description

We temporarily evict the BO attached to this range. This necessitatesevicting all user-mode queues of the process.

intamdgpu_mn_register(struct amdgpu_bo * bo, unsigned long addr)¶: register a BO for notifier updates

Parameters

structamdgpu_bo*bo: amdgpu buffer object
unsignedlongaddr: userptr addr we should monitor

Description

Registers a mmu_notifier for the given BO at the specified address.Returns 0 on success, -ERRNO if anything goes wrong.

voidamdgpu_mn_unregister(struct amdgpu_bo * bo)¶: unregister a BO for notifier updates

Parameters

structamdgpu_bo*bo: amdgpu buffer object

Description

Remove any registration of mmu notifier updates from the buffer object.

AMDGPU Virtual Memory¶

GPUVM is similar to the legacy gart on older asics, howeverrather than there being a single global gart tablefor the entire GPU, there are multiple VM page tables activeat any given time. The VM page tables can contain a mixvram pages and system memory pages and system memory pagescan be mapped as snooped (cached system pages) or unsnooped(uncached system pages).Each VM has an ID associated with it and there is a page tableassociated with each VMID. When execting a command buffer,the kernel tells the the ring what VMID to use for that commandbuffer. VMIDs are allocated dynamically as commands are submitted.The userspace drivers maintain their own address space and the kernelsets up their pages tables accordingly when they submit theircommand buffers and a VMID is assigned.Cayman/Trinity support up to 8 active VMs at any given time;SI supports 16.

structamdgpu_prt_cb¶: Helper to disable partial resident texture feature from a fence callback

Definition

struct amdgpu_prt_cb {  struct amdgpu_device *adev;  struct dma_fence_cb cb;};

Members

adev: amdgpu device
cb: callback

unsignedamdgpu_vm_level_shift(struct amdgpu_device * adev, unsigned level)¶: return the addr shift for each level

Parameters

structamdgpu_device*adev: amdgpu_device pointer
unsignedlevel: VMPT level

Return

The number of bits the pfn needs to be right shifted for a level.

unsignedamdgpu_vm_num_entries(struct amdgpu_device * adev, unsigned level)¶: return the number of entries in a PD/PT

Parameters

structamdgpu_device*adev: amdgpu_device pointer
unsignedlevel: VMPT level

Return

The number of entries in a page directory or page table.

unsignedamdgpu_vm_num_ats_entries(struct amdgpu_device * adev)¶: return the number of ATS entries in the root PD

Parameters

structamdgpu_device*adev: amdgpu_device pointer

Return

The number of entries in the root page directory which needs the ATS setting.

uint32_tamdgpu_vm_entries_mask(struct amdgpu_device * adev, unsigned int level)¶: the mask to get the entry number of a PD/PT

Parameters

structamdgpu_device*adev: amdgpu_device pointer
unsignedintlevel: VMPT level

Return

The mask to extract the entry number of a PD/PT from an address.

unsignedamdgpu_vm_bo_size(struct amdgpu_device * adev, unsigned level)¶: returns the size of the BOs in bytes

Parameters

structamdgpu_device*adev: amdgpu_device pointer
unsignedlevel: VMPT level

Return

The size of the BO for a page directory or page table in bytes.

voidamdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is evicted

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is evicted

Description

State for PDs/PTs and per VM BOs which are not at the location they shouldbe.

voidamdgpu_vm_bo_moved(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is moved

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is moved

Description

State for per VM BOs which are moved, but that change is not yet reflectedin the page tables.

voidamdgpu_vm_bo_idle(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is idle

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is now idle

Description

State for PDs/PTs and per VM BOs which have gone through the state machineand are now idle.

voidamdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is invalidated

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is now invalidated

Description

State for normal BOs which are invalidated and that change not yet reflectedin the PTs.

voidamdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is reloacted

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is relocated

Description

State for PDs/PTs which needs to update their parent PD.For the root PD, just move to idle state.

voidamdgpu_vm_bo_done(struct amdgpu_vm_bo_base * vm_bo)¶: vm_bo is done

Parameters

structamdgpu_vm_bo_base*vm_bo: vm_bo which is now done

Description

State for normal BOs which are invalidated and that change has been updatedin the PTs.

voidamdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base * base, struct amdgpu_vm * vm, struct amdgpu_bo * bo)¶: Adds bo to the list of bos associated with the vm

Parameters

structamdgpu_vm_bo_base*base: base structure for tracking BO usage in a VM
structamdgpu_vm*vm: vm to which bo is to be added
structamdgpu_bo*bo: amdgpu buffer object

Description

Initialize a bo_va_base structure and add it to the appropriate lists

struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt * pt)¶: get the parent page directory

Parameters

structamdgpu_vm_pt*pt: child page table

Description

Helper to get the parent entry for the child page table. NULL if we are atthe root page directory.

voidamdgpu_vm_pt_start(struct amdgpu_device * adev, struct amdgpu_vm * vm, uint64_t start, struct amdgpu_vm_pt_cursor * cursor)¶: start PD/PT walk

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: amdgpu_vm structure
uint64_tstart: start address of the walk
structamdgpu_vm_pt_cursor*cursor: state to initialize

Description

Initialize a amdgpu_vm_pt_cursor to start a walk.

boolamdgpu_vm_pt_descendant(struct amdgpu_device * adev, struct amdgpu_vm_pt_cursor * cursor)¶: go to child node

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm_pt_cursor*cursor: current state

Description

Walk to the child node of the current node.

Return

True if the walk was possible, false otherwise.

boolamdgpu_vm_pt_sibling(struct amdgpu_device * adev, struct amdgpu_vm_pt_cursor * cursor)¶: go to sibling node

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm_pt_cursor*cursor: current state

Description

Walk to the sibling node of the current node.

Return

True if the walk was possible, false otherwise.

boolamdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor * cursor)¶: go to parent node

Parameters

structamdgpu_vm_pt_cursor*cursor: current state

Description

Walk to the parent node of the current node.

Return

True if the walk was possible, false otherwise.

voidamdgpu_vm_pt_next(struct amdgpu_device * adev, struct amdgpu_vm_pt_cursor * cursor)¶: get next PD/PT in hieratchy

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm_pt_cursor*cursor: current state

Description

Walk the PD/PT tree to the next node.

voidamdgpu_vm_pt_first_dfs(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_vm_pt_cursor * start, struct amdgpu_vm_pt_cursor * cursor)¶: start a deep first search

Parameters

structamdgpu_device*adev: amdgpu_device structure
structamdgpu_vm*vm: amdgpu_vm structure
structamdgpu_vm_pt_cursor*start: optional cursor to start with
structamdgpu_vm_pt_cursor*cursor: state to initialize

Description

Starts a deep first traversal of the PD/PT tree.

boolamdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor * start, struct amdgpu_vm_pt * entry)¶: check if the deep first search should continue

Parameters

structamdgpu_vm_pt_cursor*start: starting point for the search
structamdgpu_vm_pt*entry: current entry

Return

True when the search should continue, false otherwise.

voidamdgpu_vm_pt_next_dfs(struct amdgpu_device * adev, struct amdgpu_vm_pt_cursor * cursor)¶: get the next node for a deep first search

Parameters

structamdgpu_device*adev: amdgpu_device structure
structamdgpu_vm_pt_cursor*cursor: current state

Description

Move the cursor to the next node in a deep first search.

voidamdgpu_vm_get_pd_bo(struct amdgpu_vm * vm, struct list_head * validated, struct amdgpu_bo_list_entry * entry)¶: add the VM PD to a validation list

Parameters

structamdgpu_vm*vm: vm providing the BOs
structlist_head*validated: head of validation list
structamdgpu_bo_list_entry*entry: entry to add

Description

Add the page directory to the list of BOs tovalidate for command submission.

voidamdgpu_vm_del_from_lru_notify(struct ttm_buffer_object * bo)¶: update bulk_moveable flag

Parameters

structttm_buffer_object*bo: BO which was removed from the LRU

Description

Make sure the bulk_moveable flag is updated when a BO is removed from theLRU.

voidamdgpu_vm_move_to_lru_tail(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: move all BOs to the end of LRU

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_vm*vm: vm providing the BOs

Description

Move all BOs to the end of LRU and remember their positions to put themtogether.

intamdgpu_vm_validate_pt_bos(struct amdgpu_device * adev, struct amdgpu_vm * vm, int (*validate)(void *p, struct amdgpu_bo *bo), void * param)¶: validate the page table BOs

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_vm*vm: vm providing the BOs
int(*)(void*p,structamdgpu_bo*bo)validate: callback to do the validation
void*param: parameter for the validation callback

Description

Validate the page table BOs on command submission if neccessary.

Return

Validation result.

boolamdgpu_vm_ready(struct amdgpu_vm * vm)¶: check VM is ready for updates

Parameters

structamdgpu_vm*vm: VM to check

Description

Check if all VM PDs/PTs are ready for updates

Return

True if eviction list is empty.

intamdgpu_vm_clear_bo(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_bo * bo, bool immediate)¶: initially clear the PDs/PTs

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: VM to clear BO from
structamdgpu_bo*bo: BO to clear
boolimmediate: use an immediate update

Description

Root PD needs to be reserved when calling this.

Return

0 on success, errno otherwise.

voidamdgpu_vm_bo_param(struct amdgpu_device * adev, struct amdgpu_vm * vm, int level, bool immediate, struct amdgpu_bo_param * bp)¶: fill in parameters for PD/PT allocation

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requesting vm
intlevel: the page table level
boolimmediate: use a immediate update
structamdgpu_bo_param*bp: resulting BO allocation parameters

intamdgpu_vm_alloc_pts(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_vm_pt_cursor * cursor, bool immediate)¶: Allocate a specific page table

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: VM to allocate page tables for
structamdgpu_vm_pt_cursor*cursor: Which page table to allocate
boolimmediate: use an immediate update

Description

Make sure a specific page table or directory is allocated.

Return

1 if page table needed to be allocated, 0 if page table was alreadyallocated, negative errno if an error occurred.

voidamdgpu_vm_free_table(struct amdgpu_vm_pt * entry)¶: fre one PD/PT

Parameters

structamdgpu_vm_pt*entry: PDE to free

voidamdgpu_vm_free_pts(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_vm_pt_cursor * start)¶: free PD/PT levels

Parameters

structamdgpu_device*adev: amdgpu device structure
structamdgpu_vm*vm: amdgpu vm structure
structamdgpu_vm_pt_cursor*start: optional cursor where to start freeing PDs/PTs

Description

Free the page directory or page table level and all sub levels.

voidamdgpu_vm_check_compute_bug(struct amdgpu_device * adev)¶: check whether asic has compute vm bug

Parameters

structamdgpu_device*adev: amdgpu_device pointer

boolamdgpu_vm_need_pipeline_sync(struct amdgpu_ring * ring, struct amdgpu_job * job)¶: Check if pipe sync is needed for job.

Parameters

structamdgpu_ring*ring: ring on which the job will be submitted
structamdgpu_job*job: job to submit

Return

True if sync is needed.

intamdgpu_vm_flush(struct amdgpu_ring * ring, struct amdgpu_job * job, bool need_pipe_sync)¶: hardware flush the vm

Parameters

structamdgpu_ring*ring: ring to use for flush
structamdgpu_job*job: related job
boolneed_pipe_sync: is pipe sync needed

Description

Emit a VM flush when it is necessary.

Return

0 on success, errno otherwise.

struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm * vm, struct amdgpu_bo * bo)¶: find the bo_va for a specific vm & bo

Parameters

structamdgpu_vm*vm: requested vm
structamdgpu_bo*bo: requested buffer object

Description

Findbo inside the requested vm.Search inside thebos vm list for the requested vmReturns the found bo_va or NULL if none is found

Object has to be reserved!

Return

Found bo_va or NULL.

uint64_tamdgpu_vm_map_gart(const dma_addr_t * pages_addr, uint64_t addr)¶: Resolve gart mapping of addr

Parameters

constdma_addr_t*pages_addr: optional DMA address to use for lookup
uint64_taddr: the unmapped addr

Description

Look up the physical address of the page that the pte resolvesto.

Return

The pointer for the page table entry.

intamdgpu_vm_update_pde(struct amdgpu_vm_update_params * params, struct amdgpu_vm * vm, struct amdgpu_vm_pt * entry)¶: update a single level in the hierarchy

Parameters

structamdgpu_vm_update_params*params: parameters for the update
structamdgpu_vm*vm: requested vm
structamdgpu_vm_pt*entry: entry to update

Description

Makes sure the requested entry in parent is up to date.

voidamdgpu_vm_invalidate_pds(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: mark all PDs as invalid

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: related vm

Description

Mark all PD level as invalid after an error.

intamdgpu_vm_update_pdes(struct amdgpu_device * adev, struct amdgpu_vm * vm, bool immediate)¶: make sure that all directories are valid

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
boolimmediate: submit immediately to the paging queue

Description

Makes sure all directories are up to date.

Return

0 for success, error for failure.

voidamdgpu_vm_fragment(struct amdgpu_vm_update_params * params, uint64_t start, uint64_t end, uint64_t flags, unsigned int * frag, uint64_t * frag_end)¶: get fragment for PTEs

Parameters

structamdgpu_vm_update_params*params: see amdgpu_vm_update_params definition
uint64_tstart: first PTE to handle
uint64_tend: last PTE to handle
uint64_tflags: hw mapping flags
unsignedint*frag: resulting fragment size
uint64_t*frag_end: end of this fragment

Description

Returns the first possible fragment for the start and end address.

intamdgpu_vm_update_ptes(struct amdgpu_vm_update_params * params, uint64_t start, uint64_t end, uint64_t dst, uint64_t flags)¶: make sure that page tables are valid

Parameters

structamdgpu_vm_update_params*params: see amdgpu_vm_update_params definition
uint64_tstart: start of GPU address range
uint64_tend: end of GPU address range
uint64_tdst: destination address to map to, the next dst inside the function
uint64_tflags: mapping flags

Description

Update the page tables in the rangestart -end.

Return

0 for success, -EINVAL for failure.

intamdgpu_vm_bo_update_mapping(struct amdgpu_device * adev, struct amdgpu_vm * vm, bool immediate, bool unlocked, structdma_resv * resv, uint64_t start, uint64_t last, uint64_t flags, uint64_t addr, dma_addr_t * pages_addr, structdma_fence ** fence)¶: update a mapping in the vm page table

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
boolimmediate: immediate submission in a page fault
boolunlocked: unlocked invalidation during MM callback
structdma_resv*resv: fences we need to sync to
uint64_tstart: start of mapped range
uint64_tlast: last mapped entry
uint64_tflags: flags for the entries
uint64_taddr: addr to set the area to
dma_addr_t*pages_addr: DMA addresses to use for mapping
structdma_fence**fence: optional resulting fence

Description

Fill in the page table entries betweenstart andlast.

Return

0 for success, -EINVAL for failure.

intamdgpu_vm_bo_split_mapping(struct amdgpu_device * adev, structdma_resv * resv, dma_addr_t * pages_addr, struct amdgpu_vm * vm, struct amdgpu_bo_va_mapping * mapping, uint64_t flags, struct amdgpu_device * bo_adev, structdrm_mm_node * nodes, structdma_fence ** fence)¶: split a mapping into smaller chunks

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structdma_resv*resv: fences we need to sync to
dma_addr_t*pages_addr: DMA addresses to use for mapping
structamdgpu_vm*vm: requested vm
structamdgpu_bo_va_mapping*mapping: mapped range and flags to use for the update
uint64_tflags: HW flags for the mapping
structamdgpu_device*bo_adev: amdgpu_device pointer that bo actually been allocated
structdrm_mm_node*nodes: array of drm_mm_nodes with the MC addresses
structdma_fence**fence: optional resulting fence

Description

Split the mapping into smaller chunks so that each update fitsinto a SDMA IB.

Return

0 for success, -EINVAL for failure.

intamdgpu_vm_bo_update(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va, bool clear)¶: update all BO mappings in the vm page table

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: requested BO and VM object
boolclear: if true clear the entries

Description

Fill in the page table entries forbo_va.

Return

0 for success, -EINVAL for failure.

voidamdgpu_vm_update_prt_state(struct amdgpu_device * adev)¶: update the global PRT state

Parameters

structamdgpu_device*adev: amdgpu_device pointer

voidamdgpu_vm_prt_get(struct amdgpu_device * adev)¶: add a PRT user

Parameters

structamdgpu_device*adev: amdgpu_device pointer

voidamdgpu_vm_prt_put(struct amdgpu_device * adev)¶: drop a PRT user

Parameters

structamdgpu_device*adev: amdgpu_device pointer

voidamdgpu_vm_prt_cb(structdma_fence * fence, structdma_fence_cb * _cb)¶: callback for updating the PRT status

Parameters

structdma_fence*fence: fence for the callback
structdma_fence_cb*_cb: the callback function

voidamdgpu_vm_add_prt_cb(struct amdgpu_device * adev, structdma_fence * fence)¶: add callback for updating the PRT status

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structdma_fence*fence: fence for the callback

voidamdgpu_vm_free_mapping(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_bo_va_mapping * mapping, structdma_fence * fence)¶: free a mapping

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
structamdgpu_bo_va_mapping*mapping: mapping to be freed
structdma_fence*fence: fence of the unmap operation

Description

Free a mapping and make sure we decrease the PRT usage count if applicable.

voidamdgpu_vm_prt_fini(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: finish all prt mappings

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm

Description

intamdgpu_vm_clear_freed(struct amdgpu_device * adev, struct amdgpu_vm * vm, structdma_fence ** fence)¶: clear freed BOs in the PT

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
structdma_fence**fence: optional resulting fence (unchanged if no work needed to be doneor if an error occurred)

Description

Make sure all freed BOs are cleared in the PT.PTs have to be reserved and mutex must be locked!

Return

0 for success.

intamdgpu_vm_handle_moved(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: handle moved BOs in the PT

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm

Description

Make sure all BOs which are moved are updated in the PTs.

PTs have to be reserved!

Return

0 for success.

struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device * adev, struct amdgpu_vm * vm, struct amdgpu_bo * bo)¶: add a bo to a specific vm

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
structamdgpu_bo*bo: amdgpu buffer object

Description

Addbo into the requested vm.Addbo to the list of bos associated with the vm

Object has to be reserved!

Return

Newly added bo_va or NULL for failure

voidamdgpu_vm_bo_insert_map(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va, struct amdgpu_bo_va_mapping * mapping)¶: insert a new mapping

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: bo_va to store the address
structamdgpu_bo_va_mapping*mapping: the mapping to insert

Description

Insert a new mapping into all structures.

intamdgpu_vm_bo_map(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va, uint64_t saddr, uint64_t offset, uint64_t size, uint64_t flags)¶: map bo inside a vm

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: bo_va to store the address
uint64_tsaddr: where to map the BO
uint64_toffset: requested offset in the BO
uint64_tsize: BO size in bytes
uint64_tflags: attributes of pages (read/write/valid/etc.)

Description

Add a mapping of the BO at the specefied addr into the VM.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_replace_map(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va, uint64_t saddr, uint64_t offset, uint64_t size, uint64_t flags)¶: map bo inside a vm, replacing existing mappings

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: bo_va to store the address
uint64_tsaddr: where to map the BO
uint64_toffset: requested offset in the BO
uint64_tsize: BO size in bytes
uint64_tflags: attributes of pages (read/write/valid/etc.)

Description

Add a mapping of the BO at the specefied addr into the VM. Replace existingmappings as we do so.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_unmap(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va, uint64_t saddr)¶: remove bo mapping from vm

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: bo_va to remove the address from
uint64_tsaddr: where to the BO is mapped

Description

Remove a mapping of the BO at the specefied addr from the VM.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_clear_mappings(struct amdgpu_device * adev, struct amdgpu_vm * vm, uint64_t saddr, uint64_t size)¶: remove all mappings in a specific range

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: VM structure to use
uint64_tsaddr: start of the range
uint64_tsize: size of the range

Description

Remove all mappings in a range, split them as appropriate.

Return

0 for success, error for failure.

struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm * vm, uint64_t addr)¶: find mapping by address

Parameters

structamdgpu_vm*vm: the requested VM
uint64_taddr: the address

Description

Find a mapping by it’s address.

Return

The amdgpu_bo_va_mapping matching for addr or NULL

voidamdgpu_vm_bo_trace_cs(struct amdgpu_vm * vm, struct ww_acquire_ctx * ticket)¶: trace all reserved mappings

Parameters

structamdgpu_vm*vm: the requested vm
structww_acquire_ctx*ticket: CS ticket

Description

Trace all mappings of BOs reserved during a command submission.

voidamdgpu_vm_bo_rmv(struct amdgpu_device * adev, struct amdgpu_bo_va * bo_va)¶: remove a bo to a specific vm

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo_va*bo_va: requested bo_va

Description

Removebo_va->bo from the requested vm.

Object have to be reserved!

boolamdgpu_vm_evictable(struct amdgpu_bo * bo)¶: check if we can evict a VM

Parameters

structamdgpu_bo*bo: A page table of the VM.

Description

Check if it is possible to evict a VM.

voidamdgpu_vm_bo_invalidate(struct amdgpu_device * adev, struct amdgpu_bo * bo, bool evicted)¶: mark the bo as invalid

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_bo*bo: amdgpu buffer object
boolevicted: is the BO evicted

Description

Markbo as invalid.

uint32_tamdgpu_vm_get_block_size(uint64_t vm_size)¶: calculate VM page table size as power of two

Parameters

uint64_tvm_size: VM size

Return

VM page table as power of two

voidamdgpu_vm_adjust_size(struct amdgpu_device * adev, uint32_t min_vm_size, uint32_t fragment_size_default, unsigned max_level, unsigned max_bits)¶: adjust vm size, block size and fragment size

Parameters

structamdgpu_device*adev: amdgpu_device pointer
uint32_tmin_vm_size: the minimum vm size in GB if it’s set auto
uint32_tfragment_size_default: Default PTE fragment size
unsignedmax_level: max VMPT level
unsignedmax_bits: max address space size in bits

longamdgpu_vm_wait_idle(struct amdgpu_vm * vm, long timeout)¶: wait for the VM to become idle

Parameters

structamdgpu_vm*vm: VM object to wait for
longtimeout: timeout to wait for VM to become idle

intamdgpu_vm_init(struct amdgpu_device * adev, struct amdgpu_vm * vm, int vm_context, unsigned int pasid)¶: initialize a vm instance

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
intvm_context: Indicates if it GFX or Compute context
unsignedintpasid: Process address space identifier

Description

Initvm fields.

Return

0 for success, error for failure.

intamdgpu_vm_check_clean_reserved(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: check if a VM is clean

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: the VM to check

Description

check all entries of the root PD, if any subsequent PDs are allocated,it means there are page table creating and filling, and is no a cleanVM

Return

0 if this VM is clean

intamdgpu_vm_make_compute(struct amdgpu_device * adev, struct amdgpu_vm * vm, unsigned int pasid)¶: Turn a GFX VM into a compute VM

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm
unsignedintpasid: pasid to use

Description

This only works on GFX VMs that don’t have any BOs added and nopage tables allocated yet.

Changes the following VM parameters:- use_cpu_for_update- pte_supports_ats- pasid (old PASID is released, because compute manages its own PASIDs)

Reinitializes the page directory to reflect the changed ATSsetting.

Return

0 for success, -errno for errors.

voidamdgpu_vm_release_compute(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: release a compute vm

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: a vm turned into compute vm by calling amdgpu_vm_make_compute

Description

This is a correspondant of amdgpu_vm_make_compute. It decouples computepasid from vm. Compute should stop use of vm after this call.

voidamdgpu_vm_fini(struct amdgpu_device * adev, struct amdgpu_vm * vm)¶: tear down a vm instance

Parameters

structamdgpu_device*adev: amdgpu_device pointer
structamdgpu_vm*vm: requested vm

Description

Tear downvm.Unbind the VM and remove all bos from the vm bo list

voidamdgpu_vm_manager_init(struct amdgpu_device * adev)¶: init the VM manager

Parameters

structamdgpu_device*adev: amdgpu_device pointer

Description

Initialize the VM manager structures

voidamdgpu_vm_manager_fini(struct amdgpu_device * adev)¶: cleanup VM manager

Parameters

structamdgpu_device*adev: amdgpu_device pointer

Description

Cleanup the VM manager and free resources.

intamdgpu_vm_ioctl(structdrm_device * dev, void * data, structdrm_file * filp)¶: Manages VMID reservation for vm hubs.

Parameters

structdrm_device*dev: drm device pointer
void*data: drm_amdgpu_vm
structdrm_file*filp: drm file pointer

Return

0 for success, -errno for errors.

voidamdgpu_vm_get_task_info(struct amdgpu_device * adev, unsigned int pasid, struct amdgpu_task_info * task_info)¶: Extracts task info for a PASID.

Parameters

structamdgpu_device*adev: drm device pointer
unsignedintpasid: PASID identifier for VM
structamdgpu_task_info*task_info: task_info to fill.

voidamdgpu_vm_set_task_info(struct amdgpu_vm * vm)¶: Sets VMs task info.

Parameters

structamdgpu_vm*vm: vm for which to set the info

boolamdgpu_vm_handle_fault(struct amdgpu_device * adev, unsigned int pasid, uint64_t addr)¶: graceful handling of VM faults.

Parameters

structamdgpu_device*adev: amdgpu device pointer
unsignedintpasid: PASID of the VM
uint64_taddr: Address of the fault

Description

Try to gracefully handle a VM fault. Return true if the fault was handled andshouldn’t be reported any more.

Interrupt Handling¶

Interrupts generated within GPU hardware raise interrupt requests that arepassed to amdgpu IRQ handler which is responsible for detecting source andtype of the interrupt and dispatching matching handlers. If handling aninterrupt requires calling kernel functions that may sleep processing isdispatched to work handlers.

If MSI functionality is not disabled by module parameter then MSIsupport will be enabled.

For GPU interrupt sources that may be driven by another driver, IRQ domainsupport is used (with mapping between virtual and hardware IRQs).

voidamdgpu_hotplug_work_func(struct work_struct * work)¶: work handler for display hotplug event

Parameters

structwork_struct*work: work struct pointer

Description

This is the hotplug event work handler (all ASICs).The work gets scheduled from the IRQ handler if therewas a hotplug interrupt. It walks through the connector tableand calls hotplug handler for each connector. After this, it sendsa DRM hotplug event to alert userspace.

This design approach is required in order to defer hotplug event handlingfrom the IRQ handler to a work handler because hotplug handler has to usemutexes which cannot be locked in an IRQ handler (sincemutex_lock maysleep).

voidamdgpu_irq_disable_all(struct amdgpu_device * adev)¶: disableall interrupts

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Disable all types of interrupts from all sources.

irqreturn_tamdgpu_irq_handler(int irq, void * arg)¶: IRQ handler

Parameters

intirq: IRQ number (unused)
void*arg: pointer to DRM device

Description

IRQ handler for amdgpu driver (all ASICs).

Return

result of handling the IRQ, as defined byirqreturn_t

voidamdgpu_irq_handle_ih1(struct work_struct * work)¶: kick of processing for IH1

Parameters

structwork_struct*work: work structure in struct amdgpu_irq

Description

Kick of processing IH ring 1.

voidamdgpu_irq_handle_ih2(struct work_struct * work)¶: kick of processing for IH2

Parameters

structwork_struct*work: work structure in struct amdgpu_irq

Description

Kick of processing IH ring 2.

boolamdgpu_msi_ok(struct amdgpu_device * adev)¶: check whether MSI functionality is enabled

Parameters

structamdgpu_device*adev: amdgpu device pointer (unused)

Description

Checks whether MSI functionality has been disabled via module parameter(all ASICs).

Return

true if MSIs are allowed to be enabled orfalse otherwise

intamdgpu_irq_init(struct amdgpu_device * adev)¶: initialize interrupt handling

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Sets up work functions for hotplug and reset interrupts, enables MSIfunctionality, initializes vblank, hotplug and reset interrupt handling.

Return

0 on success or error code on failure

voidamdgpu_irq_fini(struct amdgpu_device * adev)¶: shut down interrupt handling

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Tears down work functions for hotplug and reset interrupts, disables MSIfunctionality, shuts down vblank, hotplug and reset interrupt handling,turns off interrupts from all sources (all ASICs).

intamdgpu_irq_add_id(struct amdgpu_device * adev, unsigned client_id, unsigned src_id, struct amdgpu_irq_src * source)¶: register IRQ source

Parameters

structamdgpu_device*adev: amdgpu device pointer
unsignedclient_id: client id
unsignedsrc_id: source id
structamdgpu_irq_src*source: IRQ source pointer

Description

Registers IRQ source on a client.

Return

0 on success or error code otherwise

voidamdgpu_irq_dispatch(struct amdgpu_device * adev, struct amdgpu_ih_ring * ih)¶: dispatch IRQ to IP blocks

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_ih_ring*ih: interrupt ring instance

Description

Dispatches IRQ to IP blocks.

intamdgpu_irq_update(struct amdgpu_device * adev, struct amdgpu_irq_src * src, unsigned type)¶: update hardware interrupt state

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_irq_src*src: interrupt source pointer
unsignedtype: type of interrupt

Description

Updates interrupt state for the specific source (all ASICs).

voidamdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)¶: update interrupt states on all sources

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Updates state of all types of interrupts on all sources on resume afterreset.

intamdgpu_irq_get(struct amdgpu_device * adev, struct amdgpu_irq_src * src, unsigned type)¶: enable interrupt

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_irq_src*src: interrupt source pointer
unsignedtype: type of interrupt

Description

Enables specified type of interrupt on the specified source (all ASICs).

Return

0 on success or error code otherwise

intamdgpu_irq_put(struct amdgpu_device * adev, struct amdgpu_irq_src * src, unsigned type)¶: disable interrupt

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_irq_src*src: interrupt source pointer
unsignedtype: type of interrupt

Description

Enables specified type of interrupt on the specified source (all ASICs).

Return

0 on success or error code otherwise

boolamdgpu_irq_enabled(struct amdgpu_device * adev, struct amdgpu_irq_src * src, unsigned type)¶: check whether interrupt is enabled or not

Parameters

structamdgpu_device*adev: amdgpu device pointer
structamdgpu_irq_src*src: interrupt source pointer
unsignedtype: type of interrupt

Description

Checks whether the given type of interrupt is enabled on the given source.

Return

true if interrupt is enabled,false if interrupt is disabled or oninvalid parameters

intamdgpu_irqdomain_map(struct irq_domain * d, unsigned int irq, irq_hw_number_t hwirq)¶: create mapping between virtual and hardware IRQ numbers

Parameters

structirq_domain*d: amdgpu IRQ domain pointer (unused)
unsignedintirq: virtual IRQ number
irq_hw_number_thwirq: hardware irq number

Description

Current implementation assigns simple interrupt handler to the given virtualIRQ.

Return

0 on success or error code otherwise

intamdgpu_irq_add_domain(struct amdgpu_device * adev)¶: create a linear IRQ domain

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Creates an IRQ domain for GPU interrupt sourcesthat may be driven by another driver (e.g., ACP).

Return

0 on success or error code otherwise

voidamdgpu_irq_remove_domain(struct amdgpu_device * adev)¶: remove the IRQ domain

Parameters

structamdgpu_device*adev: amdgpu device pointer

Description

Removes the IRQ domain for GPU interrupt sourcesthat may be driven by another driver (e.g., ACP).

unsignedamdgpu_irq_create_mapping(struct amdgpu_device * adev, unsigned src_id)¶: create mapping between domain Linux IRQs

Parameters

structamdgpu_device*adev: amdgpu device pointer
unsignedsrc_id: IH source id

Description

Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQUse this for components that generate a GPU interrupt, but are drivenby a different driver (e.g., ACP).

Return

Linux IRQ

AMDGPU XGMI Support¶

XGMI is a high speed interconnect that joins multiple GPU cardsinto a homogeneous memory space that is organized by a collectivehive ID and individual node IDs, both of which are 64-bit numbers.

The file xgmi_device_id contains the unique per GPU device ID andis stored in the /sys/class/drm/card${cardno}/device/ directory.

Inside the device directory a sub-directory ‘xgmi_hive_info’ iscreated which contains the hive ID and the list of nodes.

The hive ID is stored in:: /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
The node information is stored in numbered directories:: /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id

Each device has their own xgmi_hive_info direction with a mirrorset of node sub-directories.

The XGMI memory space is built by contiguously adding the power oftwo padded VRAM space from each node to each other.

AMDGPU RAS Support¶

The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) anddebugfs (for error injection).

RAS debugfs/sysfs Control and Error Injection Interfaces¶

It accepts struct ras_debug_if who has two members.

First member: ras_debug_if::head or ras_debug_if::inject.

head is used to indicate which IP block will be under control.

head has four members, they are block, type, sub_block_index, name.block: which IP will be under control.type: what kind of error will be enabled/disabled/injected.sub_block_index: some IPs have subcomponets. say, GFX, sDMA.name: the name of IP.

inject has two more members than head, they are address, value.As their names indicate, inject operation will write thevalue to the address.

The second member: struct ras_debug_if::op.It has three kinds of operations.

0: disable RAS on the block. Take ::head as its data.
1: enable RAS on the block. Take ::head as its data.
2: inject errors on the block. Take ::inject as its data.

How to use the interface?

Programs

Copy the struct ras_debug_if in your codes and initialize it.Write the struct to the control node.

Shells

echo op block[error[sub_block address value]] > .../ras/ras_ctrl

Parameters:

op: disable, enable, inject: disable: only block is neededenable: block and error are neededinject: error, address, value are needed
block: umc, sdma, gfx, ………: see ras_block_string[] for details
error: ue, ce: ue: multi_uncorrectablece: single_correctable
sub_block:: sub block index, pass 0 if there is no sub block

here are some examples for bash commands:

echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrlecho inject umc ce000 > /sys/kernel/debug/dri/0/ras/ras_ctrlecho disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl

How to check the result?

For disable/enable, please check ras features at/sys/class/drm/card[0/1/2…]/device/ras/features

For inject, please check corresponding err count at/sys/class/drm/card[0/1/2…]/device/ras/[gfx/sdma/…]_err_count

Note

Operations are only allowed on blocks which are supported.Please check ras mask at /sys/module/amdgpu/parameters/ras_maskto see which blocks support RAS on a particular asic.

RAS Reboot Behavior for Unrecoverable Errors¶

Normally when there is an uncorrectable error, the driver will resetthe GPU to recover. However, in the event of an unrecoverable error,the driver provides an interface to reboot the system automaticallyin that event.

The following file in debugfs provides that interface:/sys/kernel/debug/dri/[0/1/2…]/ras/auto_reboot

Usage:

echotrue > .../ras/auto_reboot

RAS Error Count sysfs Interface¶

It allows the user to read the error count for each IP block on the gpu through/sys/class/drm/card[0/1/2…]/device/ras/[gfx/sdma/…]_err_count

It outputs the multiple lines which report the uncorrected (ue) and corrected(ce) error counts.

The format of one line is below,

[ce|ue]: count

Example:

ue:0ce:1

RAS EEPROM debugfs Interface¶

Some boards contain an EEPROM which is used to persistently store a list ofbad pages which experiences ECC errors in vram. This interface providesa way to reset the EEPROM, e.g., after testing error injection.

Usage:

echo1 > ../ras/ras_eeprom_reset

will reset EEPROM table to 0 entries.

RAS VRAM Bad Pages sysfs Interface¶

It allows user to read the bad pages of vram on the gpu through/sys/class/drm/card[0/1/2…]/device/ras/gpu_vram_bad_pages

It outputs multiple lines, and each line stands for one gpu page.

The format of one line is below,gpu pfn : gpu page size : flags

gpu pfn and gpu page size are printed in hex format.flags can be one of below character,

R: reserved, this gpu page is reserved and not able to use.

P: pending for reserve, this gpu page is marked as bad, will be reservedin next window of page_reserve.

F: unable to reserve. this gpu page can’t be reserved due to some reasons.

Examples:

0x00000001 : 0x00001000 : R0x00000002 : 0x00001000 : P

Sample Code¶

Sample code for testing error injection can be found here:https://cgit.freedesktop.org/mesa/drm/tree/tests/amdgpu/ras_tests.c

This is part of the libdrm amdgpu unit tests which cover several areas of the GPU.There are four sets of tests:

RAS Basic Test

The test verifies the RAS feature enabled status and makes sure the necessary sysfs and debugfs filesare present.

RAS Query Test

This test checks the RAS availability and enablement status for each supported IP block as well asthe error counts.

RAS Inject Test

This test injects errors for each IP.

RAS Disable Test

This test tests disabling of RAS features for each IP block.

GPU Power/Thermal Controls and Monitoring¶

This section covers hwmon and power/thermal controls.

HWMON Interfaces¶

The amdgpu driver exposes the following sensor interfaces:

GPU temperature (via the on-die sensor)
GPU voltage
Northbridge voltage (APUs only)
GPU power
GPU fan
GPU gfx/compute engine clock
GPU memory clock (dGPU only)

hwmon interfaces for GPU temperature:

temp[1-3]_input: the on die GPU temperature in millidegrees Celsius- temp2_input and temp3_input are supported on SOC15 dGPUs only
temp[1-3]_label: temperature channel label- temp2_label and temp3_label are supported on SOC15 dGPUs only
temp[1-3]_crit: temperature critical max value in millidegrees Celsius- temp2_crit and temp3_crit are supported on SOC15 dGPUs only
temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius- temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius- these are supported on SOC15 dGPUs only

hwmon interfaces for GPU voltage:

in0_input: the voltage on the GPU in millivolts
in1_input: the voltage on the Northbridge in millivolts

hwmon interfaces for GPU power:

power1_average: average power used by the GPU in microWatts
power1_cap_min: minimum cap supported in microWatts
power1_cap_max: maximum cap supported in microWatts
power1_cap: selected power cap in microWatts

hwmon interfaces for GPU fan:

pwm1: pulse width modulation fan level (0-255)
pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
pwm1_min: pulse width modulation fan control minimum level (0)
pwm1_max: pulse width modulation fan control maximum level (255)
fan1_min: an minimum value Unit: revolution/min (RPM)
fan1_max: an maxmum value Unit: revolution/max (RPM)
fan1_input: fan speed in RPM
fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable

hwmon interfaces for GPU clocks:

freq1_input: the gfx/compute clock in hertz
freq2_input: the memory clock in hertz

You can use hwmon tools like sensors to view this information on your system.

GPU sysfs Power State Interfaces¶

GPU power controls are exposed via sysfs files.

power_dpm_state¶

The power_dpm_state file is a legacy interface and is only provided forbackwards compatibility. The amdgpu driver provides a sysfs API for adjustingcertain power related parameters. The file power_dpm_state is used for this.It accepts the following arguments:

battery
balanced
performance

battery

On older GPUs, the vbios provided a special power state for batteryoperation. Selecting battery switched to this state. This is nolonger provided on newer GPUs so the option does nothing in that case.

balanced

On older GPUs, the vbios provided a special power state for balancedoperation. Selecting balanced switched to this state. This is nolonger provided on newer GPUs so the option does nothing in that case.

performance

On older GPUs, the vbios provided a special power state for performanceoperation. Selecting performance switched to this state. This is nolonger provided on newer GPUs so the option does nothing in that case.

power_dpm_force_performance_level¶

The amdgpu driver provides a sysfs API for adjusting certain powerrelated parameters. The file power_dpm_force_performance_level isused for this. It accepts the following arguments:

auto
low
high
manual
profile_standard
profile_min_sclk
profile_min_mclk
profile_peak

auto

When auto is selected, the driver will attempt to dynamically selectthe optimal power profile for current conditions in the driver.

low

When low is selected, the clocks are forced to the lowest power state.

high

When high is selected, the clocks are forced to the highest power state.

manual

When manual is selected, the user can manually adjust which power statesare enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,and pp_dpm_pcie files and adjust the power state transition heuristicsvia the pp_power_profile_mode sysfs file.

profile_standardprofile_min_sclkprofile_min_mclkprofile_peak

When the profiling modes are selected, clock and power gating aredisabled and the clocks are set for different profiling cases. Thismode is recommended for profiling specific work loads where you donot want clock or power gating for clock fluctuation to interferewith your results. profile_standard sets the clocks to a fixed clocklevel which varies from asic to asic. profile_min_sclk forces the sclkto the lowest level. profile_min_mclk forces the mclk to the lowest level.profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.

pp_table¶

The amdgpu driver provides a sysfs API for uploading new powerplaytables. The file pp_table is used for this. Reading the filewill dump the current power play table. Writing to the filewill attempt to upload a new powerplay table and re-initializepowerplay using that new table.

pp_od_clk_voltage¶

The amdgpu driver provides a sysfs API for adjusting the clocks and voltagesin each power level within a power state. The pp_od_clk_voltage is used forthis.

< For Vega10 and previous ASICs >

Reading the file will display:

a list of engine clock levels and voltages labeled OD_SCLK
a list of memory clock levels and voltages labeled OD_MCLK
a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE

To manually adjust these settings, first select manual usingpower_dpm_force_performance_level. Enter a new value for eachlevel by writing a string that contains “s/m level clock voltage” tothe file. E.g., “s 1 500 820” will update sclk level 1 to be 500 MHzat 820 mV; “m 0 350 810” will update mclk level 0 to be 350 MHz at810 mV. When you have edited all of the states as needed, write“c” (commit) to the file to commit your changes. If you want to reset to thedefault power levels, write “r” (reset) to the file to reset them.

< For Vega20 and newer ASICs >

Reading the file will display:

minimum and maximum engine clock labeled OD_SCLK
maximum memory clock labeled OD_MCLK
three <frequency, voltage> points labeled OD_VDDC_CURVE.They can be used to calibrate the sclk voltage curve.
a list of valid ranges for sclk, mclk, and voltage curve pointslabeled OD_RANGE

To manually adjust these settings:

First select manual using power_dpm_force_performance_level
For clock frequency setting, enter a new value by writing astring that contains “s/m index clock” to the file. The indexshould be 0 if to set minimum clock. And 1 if to set maximumclock. E.g., “s 0 500” will update minimum sclk to be 500 MHz.“m 1 800” will update maximum mclk to be 800Mhz.
For sclk voltage curve, enter the new values by writing astring that contains “vc point clock voltage” to the file. Thepoints are indexed by 0, 1 and 2. E.g., “vc 0 300 600” willupdate point1 with clock set as 300Mhz and voltage as600mV. “vc 2 1000 1000” will update point3 with clock setas 1000Mhz and voltage 1000mV.
When you have edited all of the states as needed, write “c” (commit)to the file to commit your changes
If you want to reset to the default power levels, write “r” (reset)to the file to reset them

pp_dpm_*¶

The amdgpu driver provides a sysfs API for adjusting what power levelsare enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used forthis.

pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available forVega10 and later ASICs.pp_dpm_fclk interface is only available for Vega20 and later ASICs.

Reading back the files will show you the available power levels withinthe power state and the clock information for those levels.

To manually adjust these states, first select manual usingpower_dpm_force_performance_level.Secondly, enter a new value for each level by inputing a string thatcontains ” echo xx xx xx > pp_dpm_sclk/mclk/pcie”E.g.,

echo"4 5 6" > pp_dpm_sclk

will enable sclk levels 4, 5, and 6.

NOTE: change to the dcefclk max dpm level is not supported now

pp_power_profile_mode¶

The amdgpu driver provides a sysfs API for adjusting the heuristicsrelated to switching between power levels in a power state. The filepp_power_profile_mode is used for this.

Reading this file outputs a list of all of the predefined power profilesand the relevant heuristics settings for that profile.

To select a profile or create a custom profile, first select manual usingpower_dpm_force_performance_level. Writing the number of a predefinedprofile to pp_power_profile_mode will enable those heuristics. Tocreate a custom set of heuristics, write a string of numbers to the filestarting with the number of the custom profile along with a settingfor each heuristic parameter. Due to differences across asic familiesthe heuristic parameters vary from family to family.

*_busy_percent¶

The amdgpu driver provides a sysfs API for reading how busy the GPUis as a percentage. The file gpu_busy_percent is used for this.The SMU firmware computes a percentage of load based on theaggregate activity level in the IP cores.

The amdgpu driver provides a sysfs API for reading how busy the VRAMis as a percentage. The file mem_busy_percent is used for this.The SMU firmware computes a percentage of load based on theaggregate activity level in the IP cores.

GPU Product Information¶

Information about the GPU can be obtained on certain cardsvia sysfs

product_name¶

The amdgpu driver provides a sysfs API for reporting the product namefor the deviceThe file serial_number is used for this and returns the product nameas returned from the FRU.NOTE: This is only available for certain server cards

product_number¶

serial_number¶

The amdgpu driver provides a sysfs API for reporting the serial numberfor the deviceThe file serial_number is used for this and returns the serial numberas returned from the FRU.NOTE: This is only available for certain server cards

unique_id¶

The amdgpu driver provides a sysfs API for providing a unique ID for the GPUThe file unique_id is used for this.This will provide a Unique ID that will persist from machine to machine

NOTE: This will only work for GFX9 and newer. This file will be absenton unsupported ASICs (GFX8 and older)

GPU Memory Usage Information¶

Various memory accounting can be accessed via sysfs

mem_info_vram_total¶

The amdgpu driver provides a sysfs API for reporting current total VRAMavailable on the deviceThe file mem_info_vram_total is used for this and returns the totalamount of VRAM in bytes

mem_info_vram_used¶

The amdgpu driver provides a sysfs API for reporting current total VRAMavailable on the deviceThe file mem_info_vram_used is used for this and returns the totalamount of currently used VRAM in bytes

mem_info_vis_vram_total¶

The amdgpu driver provides a sysfs API for reporting current totalvisible VRAM available on the deviceThe file mem_info_vis_vram_total is used for this and returns the totalamount of visible VRAM in bytes

mem_info_vis_vram_used¶

The amdgpu driver provides a sysfs API for reporting current total ofused visible VRAMThe file mem_info_vis_vram_used is used for this and returns the totalamount of currently used visible VRAM in bytes

mem_info_gtt_total¶

The amdgpu driver provides a sysfs API for reporting current total size ofthe GTT.The file mem_info_gtt_total is used for this, and returns the total size ofthe GTT block, in bytes

mem_info_gtt_used¶

The amdgpu driver provides a sysfs API for reporting current total amount ofused GTT.The file mem_info_gtt_used is used for this, and returns the current usedsize of the GTT block, in bytes

PCIe Accounting Information¶

pcie_bw¶

The amdgpu driver provides a sysfs API for estimating how much datahas been received and sent by the GPU in the last second through PCIe.The file pcie_bw is used for this.The Perf counters count the number of received and sent messages and returnthose values, as well as the maximum payload size of a PCIe packet (mps).Note that it is not possible to easily and quickly obtain the size of eachpacket transmitted, so we output the max payload size (mps) to allow forquick estimation of the PCIe bandwidth usage

pcie_replay_count¶

The amdgpu driver provides a sysfs API for reporting the total numberof PCIe replays (NAKs)The file pcie_replay_count is used for this and returns the totalnumber of replays as a sum of the NAKs generated and NAKs received

Movatterモバイル変換

drm/amdgpu AMDgpu driver¶

Module Parameters¶

Core Driver Infrastructure¶

Memory Domains¶

Buffer Objects¶

PRIME Buffer Sharing¶

MMU Notifier¶

AMDGPU Virtual Memory¶

Interrupt Handling¶

AMDGPU XGMI Support¶

AMDGPU RAS Support¶

RAS debugfs/sysfs Control and Error Injection Interfaces¶

RAS Reboot Behavior for Unrecoverable Errors¶

RAS Error Count sysfs Interface¶

RAS EEPROM debugfs Interface¶

RAS VRAM Bad Pages sysfs Interface¶

Sample Code¶

GPU Power/Thermal Controls and Monitoring¶

HWMON Interfaces¶

GPU sysfs Power State Interfaces¶

power_dpm_state¶

power_dpm_force_performance_level¶

pp_table¶

pp_od_clk_voltage¶

pp_dpm_*¶

pp_power_profile_mode¶

*_busy_percent¶

GPU Product Information¶

product_name¶

product_number¶

serial_number¶

unique_id¶

GPU Memory Usage Information¶

mem_info_vram_total¶

mem_info_vram_used¶

mem_info_vis_vram_total¶

mem_info_vis_vram_used¶

mem_info_gtt_total¶

mem_info_gtt_used¶

PCIe Accounting Information¶

pcie_bw¶

pcie_replay_count¶