Lifecycle¶

DM (and consequently DC) is registered in the amdgpu base driver as a IPblock. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added tothe base driver’s device list to be initialized and torn down accordingly.

The functions to do so are provided as hooks instructamd_ip_funcs.

intdm_hw_init(void * handle)¶

Initialize DC device

Parameters

void*handle

The base driver device containing the amdgpu_dm device.

Description

Initialize thestructamdgpu_display_manager device. This involves callingthe initializers of each DM component, then populating the struct with them.

Although the function implies hardware initialization, both hardware andsoftware are initialized here. Splitting them out to their relevant inithooks is a future TODO item.

Some notable things that are initialized here:

• Display Core, both software and hardware
• DC modules that we need (freesync and color management)
• DRM software states
• Interrupt sources and handlers
• Vblank support
• Debug FS entries, if enabled

intdm_hw_fini(void * handle)¶

Teardown DC device

Parameters

void*handle

The base driver device containing the amdgpu_dm device.

Description

Teardown components withinstructamdgpu_display_manager that requirecleanup. This involves cleaning up the DRM device, DC, and any modules thatwere loaded. Also flush IRQ workqueues and disable them.

Interrupts¶

DM provides another layer of IRQ management on top of what the base driveralready provides. This is something that could be cleaned up, and is afuture TODO item.

The base driver provides IRQ source registration with DRM, handlerregistration into the base driver’s IRQ table, and a handler callbackamdgpu_irq_handler(), with which DRM calls on interrupts. This generichandler looks up the IRQ table, and calls the respectiveamdgpu_irq_src_funcs.process hookups.

What DM provides on top are two IRQ tables specifically for top-half andbottom-half IRQ handling, with the bottom-half implementing workqueues:

• amdgpu_display_manager.irq_handler_list_high_tab
• amdgpu_display_manager.irq_handler_list_low_tab

They override the base driver’s IRQ table, and the effect can be seenin the hooks that DM provides foramdgpu_irq_src_funcs.process. Theyare all set to the DM generic handleramdgpu_dm_irq_handler(), which looks upDM’s IRQ tables. However, in order for base driver to recognize this hook, DMstill needs to register the IRQ with the base driver. Seedce110_register_irq_handlers() and dcn10_register_irq_handlers().

To expose DC’s hardware interrupt toggle to the base driver, DM implementsamdgpu_irq_src_funcs.set hooks. Base driver calls it throughamdgpu_irq_update() to enable or disable the interrupt.

structamdgpu_dm_irq_handler_data¶

Data for DM interrupt handlers.

Definition

struct amdgpu_dm_irq_handler_data {  struct list_head list;  interrupt_handler handler;  void *handler_arg;  struct amdgpu_display_manager *dm;  enum dc_irq_source irq_source;};

Members

list

Linked list entry referencing the next/previous handler

handler

Handler function

handler_arg

Argument passed to the handler when triggered

dm

DM which this handler belongs to

irq_source

DC interrupt source that this handler is registered for

voiddm_irq_work_func(struct work_struct * work)¶

Handle an IRQ outside of the interrupt handler proper.

Parameters

structwork_struct*work

work struct

void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device * adev, struct dc_interrupt_params * int_params, void (*ih)(void *), void * handler_args)¶

Register a handler within DM.

Parameters

structamdgpu_device*adev

The base driver device containing the DM device.

structdc_interrupt_params*int_params

Interrupt parameters containing the source, and handler context

void(*)(void*)ih

Function pointer to the interrupt handler to register

void*handler_args

Arguments passed to the handler when the interrupt occurs

Description

Register an interrupt handler for the given IRQ source, under the givencontext. The context can either be high or low. High context handlers areexecuted directly within ISR context, while low context is executed within aworkqueue, thereby allowing operations that sleep.

Registered handlers are called in a FIFO manner, i.e. the most recentlyregistered handler will be called first.

Return

Handler datastructamdgpu_dm_irq_handler_data containing the IRQ

source, handler function, and args

voidamdgpu_dm_irq_unregister_interrupt(struct amdgpu_device * adev, enum dc_irq_source irq_source, void * ih)¶

Remove a handler from the DM IRQ table

Parameters

structamdgpu_device*adev

The base driver device containing the DM device

enumdc_irq_sourceirq_source

IRQ source to remove the given handler from

void*ih

Function pointer to the interrupt handler to unregister

Description

Go through both low and high context IRQ tables, and find the given handlerfor the given irq source. If found, remove it. Otherwise, do nothing.

intamdgpu_dm_irq_init(struct amdgpu_device * adev)¶

Initialize DM IRQ management

Parameters

structamdgpu_device*adev

The base driver device containing the DM device

Description

Initialize DM’s high and low context IRQ tables.

The N by M table contains N IRQ sources, with Mstructamdgpu_dm_irq_handler_data hooked together in a linked list. Thelist_heads are initialized here. When an interrupt n is triggered, all mhandlers are called in sequence, FIFO according to registration order.

The low context table requires special steps to initialize, since handlerswill be deferred to a workqueue. Seestructirq_list_head.

voidamdgpu_dm_irq_fini(struct amdgpu_device * adev)¶

Tear down DM IRQ management

Parameters

structamdgpu_device*adev

The base driver device containing the DM device

Description

Flush all work within the low context IRQ table.

intamdgpu_dm_irq_handler(struct amdgpu_device * adev, struct amdgpu_irq_src * source, struct amdgpu_iv_entry * entry)¶

Generic DM IRQ handler

Parameters

structamdgpu_device*adev

amdgpu base driver device containing the DM device

structamdgpu_irq_src*source

Unused

structamdgpu_iv_entry*entry

Data about the triggered interrupt

Description

Calls all registered high irq work immediately, and schedules work for lowirq. The DM IRQ table is used to find the corresponding handlers.

voidamdgpu_dm_hpd_init(struct amdgpu_device * adev)¶

hpd setup callback.

Parameters

structamdgpu_device*adev

amdgpu_device pointer

Description

Setup the hpd pins used by the card (evergreen+).Enable the pin, set the polarity, and enable the hpd interrupts.

voidamdgpu_dm_hpd_fini(struct amdgpu_device * adev)¶

hpd tear down callback.

Parameters

structamdgpu_device*adev

amdgpu_device pointer

Description

Tear down the hpd pins used by the card (evergreen+).Disable the hpd interrupts.

voiddm_pflip_high_irq(void * interrupt_params)¶

Handle pageflip interrupt

Parameters

void*interrupt_params

ignored

Description

Handles the pageflip interrupt by notifying all interested partiesthat the pageflip has been completed.

voiddm_crtc_high_irq(void * interrupt_params)¶

Handles CRTC interrupt

Parameters

void*interrupt_params

used for determining the CRTC instance

Description

Handles the CRTC/VSYNC interrupt by notfying DRM’s VBLANKevent handler.

Atomic Implementation¶

WIP

voidamdgpu_dm_atomic_commit_tail(structdrm_atomic_state * state)¶

AMDgpu DM’s commit tail implementation.

Parameters

structdrm_atomic_state*state

The atomic state to commit

Description

This will tell DC to commit the constructed DC state from atomic_check,programming the hardware. Any failures here implies a hardware failure, sinceatomic check should have filtered anything non-kosher.

intamdgpu_dm_atomic_check(structdrm_device * dev, structdrm_atomic_state * state)¶

Atomic check implementation for AMDgpu DM.

Parameters

structdrm_device*dev

The DRM device

structdrm_atomic_state*state

The atomic state to commit

Description

Validate that the given atomic state is programmable by DC into hardware.This involves constructing astructdc_state reflecting the new hardwarestate we wish to commit, then querying DC to see if it is programmable. It’simportant not to modify the existing DC state. Otherwise, atomic_checkmay unexpectedly commit hardware changes.

When validating the DC state, it’s important that the right locks areacquired. For full updates case which removes/adds/updates streams on oneCRTC while flipping on another CRTC, acquiring global lock will guaranteethat any such full update commit will wait for completion of any outstandingflip using DRMs synchronization events. Seedm_determine_update_type_for_commit()

Note that DM adds the affected connectors for all CRTCs in state, when thatmight not seem necessary. This is because DC stream creation requires theDC sink, which is tied to the DRM connector state. Cleaning this up shouldbe possible but non-trivial - a possible TODO item.

Return

-Error code if validation failed.