Atomic Type And Operations¶

The atomic_t type should be defined as a signed integer andthe atomic_long_t type as a signed long integer. Also, they shouldbe made opaque such that any kind of cast to a normal C integer typewill fail. Something like the following should suffice:

typedef struct { int counter; } atomic_t;typedef struct { long counter; } atomic_long_t;

Historically, counter has been declared volatile. This is now discouraged.SeeDocumentation/process/volatile-considered-harmful.rst for the complete rationale.

local_t is very similar to atomic_t. If the counter is per CPU and onlyupdated by one CPU, local_t is probably more appropriate. Please seeDocumentation/core-api/local_ops.rst for the semantics oflocal_t.

The first operations to implement for atomic_t’s are the initializers andplain writes.

#define ATOMIC_INIT(i)          { (i) }#define atomic_set(v, i)        ((v)->counter = (i))

The first macro is used in definitions, such as:

static atomic_t my_counter = ATOMIC_INIT(1);

The initializer is atomic in that the return values of the atomic operationsare guaranteed to be correct reflecting the initialized value if theinitializer is used before runtime. If the initializer is used at runtime, aproper implicit or explicit read memory barrier is needed before reading thevalue with atomic_read from another thread.

As with all of theatomic_ interfaces, replace the leadingatomic_withatomic_long_ to operate on atomic_long_t.

The second interface can be used at runtime, as in:

struct foo { atomic_t counter; };...struct foo *k;k = kmalloc(sizeof(*k), GFP_KERNEL);if (!k)        return -ENOMEM;atomic_set(&k->counter, 0);

The setting is atomic in that the return values of the atomic operations byall threads are guaranteed to be correct reflecting either the value that hasbeen set with this operation or set with another operation. A proper implicitor explicit memory barrier is needed before the value set with the operationis guaranteed to be readable with atomic_read from another thread.

Next, we have:

#define atomic_read(v)  ((v)->counter)

which simply reads the counter value currently visible to the calling thread.The read is atomic in that the return value is guaranteed to be one of thevalues initialized or modified with the interface operations if a properimplicit or explicit memory barrier is used after possible runtimeinitialization by any other thread and the value is modified only with theinterface operations. atomic_read does not guarantee that the runtimeinitialization by any other thread is visible yet, so the user of theinterface must take care of that with a proper implicit or explicit memorybarrier.

Properly aligned pointers, longs, ints, and chars (and unsignedequivalents) may be atomically loaded from and stored to in the samesense as described for atomic_read() and atomic_set(). The READ_ONCE()and WRITE_ONCE() macros should be used to prevent the compiler from usingoptimizations that might otherwise optimize accesses out of existence onthe one hand, or that might create unsolicited accesses on the other.

For example consider the following code:

while (a > 0)        do_something();

If the compiler can prove that do_something() does not store to thevariable a, then the compiler is within its rights transforming this tothe following:

if (a > 0)        for (;;)                do_something();

If you don’t want the compiler to do this (and you probably don’t), thenyou should use something like the following:

while (READ_ONCE(a) > 0)        do_something();

Alternatively, you could place a barrier() call in the loop.

For another example, consider the following code:

tmp_a = a;do_something_with(tmp_a);do_something_else_with(tmp_a);

If the compiler can prove that do_something_with() does not store to thevariable a, then the compiler is within its rights to manufacture anadditional load as follows:

tmp_a = a;do_something_with(tmp_a);tmp_a = a;do_something_else_with(tmp_a);

This could fatally confuse your code if it expected the same valueto be passed to do_something_with() and do_something_else_with().

The compiler would be likely to manufacture this additional load ifdo_something_with() was an inline function that made very heavy useof registers: reloading from variable a could save a flush to thestack and later reload. To prevent the compiler from attacking yourcode in this manner, write the following:

tmp_a = READ_ONCE(a);do_something_with(tmp_a);do_something_else_with(tmp_a);

For a final example, consider the following code, assuming that thevariable a is set at boot time before the second CPU is brought onlineand never changed later, so that memory barriers are not needed:

if (a)        b = 9;else        b = 42;

The compiler is within its rights to manufacture an additional storeby transforming the above code into the following:

b = 42;if (a)        b = 9;

This could come as a fatal surprise to other code running concurrentlythat expected b to never have the value 42 if a was zero. To preventthe compiler from doing this, write something like:

if (a)        WRITE_ONCE(b, 9);else        WRITE_ONCE(b, 42);

Don’t even -think- about doing this without proper use of memory barriers,locks, or atomic operations if variable a can change at runtime!

Now, we move onto the atomic operation interfaces typically implemented withthe help of assembly code.

void atomic_add(int i, atomic_t *v);void atomic_sub(int i, atomic_t *v);void atomic_inc(atomic_t *v);void atomic_dec(atomic_t *v);

These four routines add and subtract integral values to/from the givenatomic_t value. The first two routines pass explicit integers bywhich to make the adjustment, whereas the latter two use an implicitadjustment value of “1”.

One very important aspect of these two routines is that they DO NOTrequire any explicit memory barriers. They need only perform theatomic_t counter update in an SMP safe manner.

Next, we have:

int atomic_inc_return(atomic_t *v);int atomic_dec_return(atomic_t *v);

These routines add 1 and subtract 1, respectively, from the givenatomic_t and return the new counter value after the operation isperformed.

Unlike the above routines, it is required that these primitivesinclude explicit memory barriers that are performed before and afterthe operation. It must be done such that all memory operations beforeand after the atomic operation calls are strongly ordered with respectto the atomic operation itself.

For example, it should behave as if a smp_mb() call existed bothbefore and after the atomic operation.

If the atomic instructions used in an implementation provide explicitmemory barrier semantics which satisfy the above requirements, that isfine as well.

Let’s move on:

int atomic_add_return(int i, atomic_t *v);int atomic_sub_return(int i, atomic_t *v);

These behave just like atomic_{inc,dec}_return() except that anexplicit counter adjustment is given instead of the implicit “1”.This means that like atomic_{inc,dec}_return(), the memory barriersemantics are required.

Next:

int atomic_inc_and_test(atomic_t *v);int atomic_dec_and_test(atomic_t *v);

These two routines increment and decrement by 1, respectively, thegiven atomic counter. They return a boolean indicating whether theresulting counter value was zero or not.

Again, these primitives provide explicit memory barrier semantics aroundthe atomic operation:

int atomic_sub_and_test(int i, atomic_t *v);

This is identical to atomic_dec_and_test() except that an explicitdecrement is given instead of the implicit “1”. This primitive mustprovide explicit memory barrier semantics around the operation:

int atomic_add_negative(int i, atomic_t *v);

The given increment is added to the given atomic counter value. A booleanis return which indicates whether the resulting counter value is negative.This primitive must provide explicit memory barrier semantics aroundthe operation.

Then:

int atomic_xchg(atomic_t *v, int new);

This performs an atomic exchange operation on the atomic variable v, settingthe given new value. It returns the old value that the atomic variable v hadjust before the operation.

atomic_xchg must provide explicit memory barriers around the operation.

int atomic_cmpxchg(atomic_t *v, int old, int new);

This performs an atomic compare exchange operation on the atomic value v,with the given old and new values. Like all atomic_xxx operations,atomic_cmpxchg will only satisfy its atomicity semantics as long as allother accesses of *v are performed through atomic_xxx operations.

atomic_cmpxchg must provide explicit memory barriers around the operation,although if the comparison fails then no memory ordering guarantees arerequired.

The semantics for atomic_cmpxchg are the same as those defined for ‘cas’below.

Finally:

int atomic_add_unless(atomic_t *v, int a, int u);

If the atomic value v is not equal to u, this function adds a to v, andreturns non zero. If v is equal to u then it returns zero. This is done asan atomic operation.

atomic_add_unless must provide explicit memory barriers around theoperation unless it fails (returns 0).

atomic_inc_not_zero, equivalent to atomic_add_unless(v, 1, 0)

If a caller requires memory barrier semantics around an atomic_toperation which does not return a value, a set of interfaces aredefined which accomplish this:

void smp_mb__before_atomic(void);void smp_mb__after_atomic(void);

Preceding a non-value-returning read-modify-write atomic operation withsmp_mb__before_atomic() and following it with smp_mb__after_atomic()provides the same full ordering that is provided by value-returningread-modify-write atomic operations.

For example, smp_mb__before_atomic() can be used like so:

obj->dead = 1;smp_mb__before_atomic();atomic_dec(&obj->ref_count);

It makes sure that all memory operations preceding the atomic_dec()call are strongly ordered with respect to the atomic counteroperation. In the above example, it guarantees that the assignment of“1” to obj->dead will be globally visible to other cpus before theatomic counter decrement.

Without the explicit smp_mb__before_atomic() call, theimplementation could legally allow the atomic counter update visibleto other cpus before the “obj->dead = 1;” assignment.

A missing memory barrier in the cases where they are required by theatomic_t implementation above can have disastrous results. Here isan example, which follows a pattern occurring frequently in the Linuxkernel. It is the use of atomic counters to implement referencecounting, and it works such that once the counter falls to zero it canbe guaranteed that no other entity can be accessing the object:

static void obj_list_add(struct obj *obj, struct list_head *head){        obj->active = 1;        list_add(&obj->list, head);}static void obj_list_del(struct obj *obj){        list_del(&obj->list);        obj->active = 0;}static void obj_destroy(struct obj *obj){        BUG_ON(obj->active);        kfree(obj);}struct obj *obj_list_peek(struct list_head *head){        if (!list_empty(head)) {                struct obj *obj;                obj = list_entry(head->next, struct obj, list);                atomic_inc(&obj->refcnt);                return obj;        }        return NULL;}void obj_poke(void){        struct obj *obj;        spin_lock(&global_list_lock);        obj = obj_list_peek(&global_list);        spin_unlock(&global_list_lock);        if (obj) {                obj->ops->poke(obj);                if (atomic_dec_and_test(&obj->refcnt))                        obj_destroy(obj);        }}void obj_timeout(struct obj *obj){        spin_lock(&global_list_lock);        obj_list_del(obj);        spin_unlock(&global_list_lock);        if (atomic_dec_and_test(&obj->refcnt))                obj_destroy(obj);}

Given the above scheme, it must be the case that the obj->activeupdate done by the obj list deletion be visible to other processorsbefore the atomic counter decrement is performed.

Otherwise, the counter could fall to zero, yet obj->active would stillbe set, thus triggering the assertion in obj_destroy(). The errorsequence looks like this:

cpu 0                           cpu 1obj_poke()                      obj_timeout()obj = obj_list_peek();... gains ref to obj, refcnt=2                                obj_list_del(obj);                                obj->active = 0 ...                                ... visibility delayed ...                                atomic_dec_and_test()                                ... refcnt drops to 1 ...atomic_dec_and_test()... refcount drops to 0 ...obj_destroy()BUG() triggers since obj->activestill seen as one                                obj->active update visibility occurs

With the memory barrier semantics required of the atomic_t operationswhich return values, the above sequence of memory visibility can neverhappen. Specifically, in the above case the atomic_dec_and_test()counter decrement would not become globally visible until theobj->active update does.

As a historical note, 32-bit Sparc used to only allow usage of24-bits of its atomic_t type. This was because it used 8 bitsas a spinlock for SMP safety. Sparc32 lacked a “compare and swap”type instruction. However, 32-bit Sparc has since been moved overto a “hash table of spinlocks” scheme, that allows the full 32-bitcounter to be realized. Essentially, an array of spinlocks areindexed into based upon the address of the atomic_t being operatedon, and that lock protects the atomic operation. Parisc uses thesame scheme.

Another note is that the atomic_t operations returning values areextremely slow on an old 386.

Atomic Bitmask¶

We will now cover the atomic bitmask operations. You will find thattheir SMP and memory barrier semantics are similar in shape and scopeto the atomic_t ops above.

Native atomic bit operations are defined to operate on objects alignedto the size of an “unsigned long” C data type, and are least of thatsize. The endianness of the bits within each “unsigned long” are thenative endianness of the cpu.

void set_bit(unsigned long nr, volatile unsigned long *addr);void clear_bit(unsigned long nr, volatile unsigned long *addr);void change_bit(unsigned long nr, volatile unsigned long *addr);

These routines set, clear, and change, respectively, the bit numberindicated by “nr” on the bit mask pointed to by “ADDR”.

They must execute atomically, yet there are no implicit memory barriersemantics required of these interfaces.

int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);

Like the above, except that these routines return a boolean whichindicates whether the changed bit was set _BEFORE_ the atomic bitoperation.

For one thing, this return value gets truncated to int in many codepaths using these interfaces, so on 64-bit if the bit is set in theupper 32-bits then testers will never see that.

One great example of where this problem crops up are the thread_infoflag operations. Routines such as test_and_set_ti_thread_flag() chopthe return value into an int. There are other places where thingslike this occur as well.

These routines, like the atomic_t counter operations returning values,must provide explicit memory barrier semantics around their execution.All memory operations before the atomic bit operation call must bemade visible globally before the atomic bit operation is made visible.Likewise, the atomic bit operation must be visible globally before anysubsequent memory operation is made visible. For example:

obj->dead = 1;if (test_and_set_bit(0, &obj->flags))        /* ... */;obj->killed = 1;

The implementation oftest_and_set_bit() must guarantee that“obj->dead = 1;” is visible to cpus before the atomic memory operationdone bytest_and_set_bit() becomes visible. Likewise, the atomicmemory operation done bytest_and_set_bit() must become visible before“obj->killed = 1;” is visible.

Finally there is the basic operation:

int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);

Which returns a boolean indicating if bit “nr” is set in the bitmaskpointed to by “addr”.

If explicit memory barriers are required around {set,clear}_bit() (which donot return a value, and thus does not need to provide memory barriersemantics), two interfaces are provided:

void smp_mb__before_atomic(void);void smp_mb__after_atomic(void);

They are used as follows, and are akin to their atomic_t operationbrothers:

/* All memory operations before this call will * be globally visible before the clear_bit(). */smp_mb__before_atomic();clear_bit( ... );/* The clear_bit() will be visible before all * subsequent memory operations. */ smp_mb__after_atomic();

There are two special bitops with lock barrier semantics (acquire/release,same as spinlocks). These operate in the same way as their non-_lock/unlockpostfixed variants, except that they are to provide acquire/release semantics,respectively. This means they can be used for bit_spin_trylock andbit_spin_unlock type operations without specifying any more barriers.

int test_and_set_bit_lock(unsigned long nr, unsigned long *addr);void clear_bit_unlock(unsigned long nr, unsigned long *addr);void __clear_bit_unlock(unsigned long nr, unsigned long *addr);

The __clear_bit_unlock version is non-atomic, however it still implementsunlock barrier semantics. This can be useful if the lock itself is protectingthe other bits in the word.

Finally, there are non-atomic versions of the bitmask operationsprovided. They are used in contexts where some other higher-level SMPlocking scheme is being used to protect the bitmask, and thus lessexpensive non-atomic operations may be used in the implementation.They have names similar to the above bitmask operation interfaces,except that two underscores are prefixed to the interface name.

void __set_bit(unsigned long nr, volatile unsigned long *addr);void __clear_bit(unsigned long nr, volatile unsigned long *addr);void __change_bit(unsigned long nr, volatile unsigned long *addr);int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr);int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr);

These non-atomic variants also do not require any special memorybarrier semantics.

The routines xchg() and cmpxchg() must provide the same exactmemory-barrier semantics as the atomic and bit operations returningvalues.

Spinlocks and rwlocks have memory barrier expectations as well.The rule to follow is simple:

1. When acquiring a lock, the implementation must make it globallyvisible before any subsequent memory operation.
2. When releasing a lock, the implementation must make it such thatall previous memory operations are globally visible before thelock release.

Which finally brings us to _atomic_dec_and_lock(). There is anarchitecture-neutral version implemented in lib/dec_and_lock.c,but most platforms will wish to optimize this in assembler.

int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);

Atomically decrement the given counter, and if will drop to zeroatomically acquire the given spinlock and perform the decrementof the counter to zero. If it does not drop to zero, do nothingwith the spinlock.

It is actually pretty simple to get the memory barrier correct.Simply satisfy the spinlock grab requirements, which is makesure the spinlock operation is globally visible before anysubsequent memory operation.

We can demonstrate this operation more clearly if we definean abstract atomic operation:

long cas(long *mem, long old, long new);

“cas” stands for “compare and swap”. It atomically:

1. Compares “old” with the value currently at “mem”.
2. If they are equal, “new” is written to “mem”.
3. Regardless, the current value at “mem” is returned.

As an example usage, here is what an atomic counter updatemight look like:

void example_atomic_inc(long *counter){        long old, new, ret;        while (1) {                old = *counter;                new = old + 1;                ret = cas(counter, old, new);                if (ret == old)                        break;        }}

Let’s use cas() in order to build a pseudo-C atomic_dec_and_lock():

int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock){        long old, new, ret;        int went_to_zero;        went_to_zero = 0;        while (1) {                old = atomic_read(atomic);                new = old - 1;                if (new == 0) {                        went_to_zero = 1;                        spin_lock(lock);                }                ret = cas(atomic, old, new);                if (ret == old)                        break;                if (went_to_zero) {                        spin_unlock(lock);                        went_to_zero = 0;                }        }        return went_to_zero;}

Now, as far as memory barriers go, as long as spin_lock()strictly orders all subsequent memory operations (includingthe cas()) with respect to itself, things will be fine.

Said another way, _atomic_dec_and_lock() must guarantee thata counter dropping to zero is never made visible before thespinlock being acquired.