Main Concepts used at the EDAC subsystem¶

There are several things to be aware of that aren’t at all obvious, likesockets, *socket sets,banks,rows,chip-select rows,channels,etc…

These are some of the many terms that are thrown about that don’t alwaysmean what people think they mean (Inconceivable!). In the interest ofcreating a common ground for discussion, terms and their definitionswill be established.

• Memory devices

The individual DRAM chips on a memory stick. These devices commonlyoutput 4 and 8 bits each (x4, x8). Grouping several of these in parallelprovides the number of bits that the memory controller expects:typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.

• Memory Stick

A printed circuit board that aggregates multiple memory devices inparallel. In general, this is the Field Replaceable Unit (FRU) whichgets replaced, in the case of excessive errors. Most often it is alsocalled DIMM (Dual Inline Memory Module).

• Memory Socket

A physical connector on the motherboard that accepts a single memorystick. Also called as “slot” on several datasheets.

• Channel

A memory controller channel, responsible to communicate with a group ofDIMMs. Each channel has its own independent control (command) and databus, and can be used independently or grouped with other channels.

• Branch

It is typically the highest hierarchy on a Fully-Buffered DIMM memorycontroller. Typically, it contains two channels. Two channels at thesame branch can be used in single mode or in lockstep mode. Whenlockstep is enabled, the cacheline is doubled, but it generally bringssome performance penalty. Also, it is generally not possible to point tojust one memory stick when an error occurs, as the error correction codeis calculated using two DIMMs instead of one. Due to that, it is capableof correcting more errors than on single mode.

• Single-channel

The data accessed by the memory controller is contained into one dimmonly. E. g. if the data is 64 bits-wide, the data flows to the CPU usingone 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3memories. FB-DIMM and RAMBUS use a different concept for channel, sothis concept doesn’t apply there.

• Double-channel

The data size accessed by the memory controller is interlaced into twodimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72bits with ECC), the data flows to the CPU using a 128 bits parallelaccess.

• Chip-select row

This is the name of the DRAM signal used to select the DRAM ranks to beaccessed. Common chip-select rows for single channel are 64 bits, fordual channel 128 bits. It may not be visible by the memory controller,as some DIMM types have a memory buffer that can hide direct access toit from the Memory Controller.

• Single-Ranked stick

A Single-ranked stick has 1 chip-select row of memory. Motherboardscommonly drive two chip-select pins to a memory stick. A single-rankedstick, will occupy only one of those rows. The other will be unused.

• Double-Ranked stick

A double-ranked stick has two chip-select rows which access differentsets of memory devices. The two rows cannot be accessed concurrently.

• Double-sided stick

DEPRECATED TERM, seeDouble-Ranked stick.

A double-sided stick has two chip-select rows which access different setsof memory devices. The two rows cannot be accessed concurrently.“Double-sided” is irrespective of the memory devices being mounted onboth sides of the memory stick.

• Socket set

All of the memory sticks that are required for a single memory access orall of the memory sticks spanned by a chip-select row. A single socketset has two chip-select rows and if double-sided sticks are used thesewill occupy those chip-select rows.

• Bank

This term is avoided because it is unclear when needing to distinguishbetween chip-select rows and socket sets.

Memory Controllers¶

Most of the EDAC core is focused on doing Memory Controller error detection.Theedac_mc_alloc(). It uses internally the structmem_ctl_infoto describe the memory controllers, with is an opaque struct for the EDACdrivers. Only the EDAC core is allowed to touch it.

enumdev_type¶

describe the type of memory DRAM chips used at the stick

Constants

DEV_UNKNOWN

Can’t be determined, or MC doesn’t support detect it

DEV_X1

1 bit for data

DEV_X2

2 bits for data

DEV_X4

4 bits for data

DEV_X8

8 bits for data

DEV_X16

16 bits for data

DEV_X32

32 bits for data

DEV_X64

64 bits for data

Description

Typical values are x4 and x8.

enumhw_event_mc_err_type¶

type of the detected error

Constants

HW_EVENT_ERR_CORRECTED

Corrected Error - Indicates that an ECCcorrected error was detected

HW_EVENT_ERR_UNCORRECTED

Uncorrected Error - Indicates an error thatcan’t be corrected by ECC, but it is notfatal (maybe it is on an unused memory area,or the memory controller could recover fromit for example, by re-trying the operation).

HW_EVENT_ERR_DEFERRED

Deferred Error - Indicates an uncorrectableerror whose handling is not urgent. This couldbe due to hardware data poisoning where thesystem can continue operation until the poisoneddata is consumed. Preemptive measures may alsobe taken, e.g. offlining pages, etc.

HW_EVENT_ERR_FATAL

Fatal Error - Uncorrected error that could notbe recovered.

HW_EVENT_ERR_INFO

Informational - The CPER spec defines a forthtype of error: informational logs.

enummem_type¶

memory types. For a more detailed reference, please seehttp://en.wikipedia.org/wiki/DRAM

Constants

MEM_EMPTY

Empty csrow

MEM_RESERVED

Reserved csrow type

MEM_UNKNOWN

Unknown csrow type

MEM_FPM

FPM - Fast Page Mode, used on systems up to 1995.

MEM_EDO

EDO - Extended data out, used on systems up to 1998.

MEM_BEDO

BEDO - Burst Extended data out, an EDO variant.

MEM_SDR

SDR - Single data rate SDRAMhttp://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memoryThey use 3 pins for chip select: Pins 0 and 2 arefor rank 0; pins 1 and 3 are for rank 1, if the memoryis dual-rank.

MEM_RDR

Registered SDR SDRAM

MEM_DDR

Double data rate SDRAMhttp://en.wikipedia.org/wiki/DDR_SDRAM

MEM_RDDR

Registered Double data rate SDRAMThis is a variant of the DDR memories.A registered memory has a buffer inside it, hidingpart of the memory details to the memory controller.

MEM_RMBS

Rambus DRAM, used on a few Pentium III/IV controllers.

MEM_DDR2

DDR2 RAM, as described at JEDEC JESD79-2F.Those memories are labeled as “PC2-” instead of “PC” todifferentiate from DDR.

MEM_FB_DDR2

Fully-Buffered DDR2, as described at JEDEC Std No. 205and JESD206.Those memories are accessed per DIMM slot, and not bya chip select signal.

MEM_RDDR2

Registered DDR2 RAMThis is a variant of the DDR2 memories.

MEM_XDR

Rambus XDRIt is an evolution of the original RAMBUS memories,created to compete with DDR2. Weren’t used on anyx86 arch, but cell_edac PPC memory controller uses it.

MEM_DDR3

DDR3 RAM

MEM_RDDR3

Registered DDR3 RAMThis is a variant of the DDR3 memories.

MEM_LRDDR3

Load-Reduced DDR3 memory.

MEM_DDR4

Unbuffered DDR4 RAM

MEM_RDDR4

Registered DDR4 RAMThis is a variant of the DDR4 memories.

MEM_LRDDR4

Load-Reduced DDR4 memory.

MEM_NVDIMM

Non-volatile RAM

enumedac_type¶

type - Error Detection and Correction capabilities and mode

Constants

EDAC_UNKNOWN

Unknown if ECC is available

EDAC_NONE

Doesn’t support ECC

EDAC_RESERVED

Reserved ECC type

EDAC_PARITY

Detects parity errors

EDAC_EC

Error Checking - no correction

EDAC_SECDED

Single bit error correction, Double detection

EDAC_S2ECD2ED

Chipkill x2 devices - do these exist?

EDAC_S4ECD4ED

Chipkill x4 devices

EDAC_S8ECD8ED

Chipkill x8 devices

EDAC_S16ECD16ED

Chipkill x16 devices

enumscrub_type¶

scrubbing capabilities

Constants

SCRUB_UNKNOWN

Unknown if scrubber is available

SCRUB_NONE

No scrubber

SCRUB_SW_PROG

SW progressive (sequential) scrubbing

SCRUB_SW_SRC

Software scrub only errors

SCRUB_SW_PROG_SRC

Progressive software scrub from an error

SCRUB_SW_TUNABLE

Software scrub frequency is tunable

SCRUB_HW_PROG

HW progressive (sequential) scrubbing

SCRUB_HW_SRC

Hardware scrub only errors

SCRUB_HW_PROG_SRC

Progressive hardware scrub from an error

SCRUB_HW_TUNABLE

Hardware scrub frequency is tunable

enumedac_mc_layer_type¶

memory controller hierarchy layer

Constants

EDAC_MC_LAYER_BRANCH

memory layer is named “branch”

EDAC_MC_LAYER_CHANNEL

memory layer is named “channel”

EDAC_MC_LAYER_SLOT

memory layer is named “slot”

EDAC_MC_LAYER_CHIP_SELECT

memory layer is named “chip select”

EDAC_MC_LAYER_ALL_MEM

memory layout is unknown. All memory is mappedas a single memory area. This is used whenretrieving errors from a firmware driven driver.

Description

This enum is used by the drivers to tell edac_mc_sysfs what name shouldbe used when describing a memory stick location.

structedac_mc_layer¶

describes the memory controller hierarchy

Definition

struct edac_mc_layer {  enum edac_mc_layer_type type;  unsigned size;  bool is_virt_csrow;};

Members

type

layer type

size

number of components per layer. For example,if the channel layer has two channels, size = 2

is_virt_csrow

This layer is part of the “csrow” when old APIcompatibility mode is enabled. Otherwise, it isa channel

structrank_info¶

contains the information for one DIMM rank

Definition

struct rank_info {  int chan_idx;  struct csrow_info *csrow;  struct dimm_info *dimm;  u32 ce_count;};

Members

chan_idx

channel number where the rank is (typically, 0 or 1)

csrow

A pointer to the chip select row structure (the parentstructure). The location of the rank is given bythe (csrow->csrow_idx, chan_idx) vector.

dimm

A pointer to the DIMM structure, where the DIMM labelinformation is stored.

ce_count

number of correctable errors for this rank

Description

FIXME: Currently, the EDAC core model will assume one DIMM per rank.

This is a bad assumption, but it makes this patch easier. Laterpatches in this series will fix this issue.

structedac_raw_error_desc¶

Raw error report structure

Definition

struct edac_raw_error_desc {  char location[LOCATION_SIZE];  char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];  long grain;  u16 error_count;  enum hw_event_mc_err_type type;  int top_layer;  int mid_layer;  int low_layer;  unsigned long page_frame_number;  unsigned long offset_in_page;  unsigned long syndrome;  const char *msg;  const char *other_detail;};

Members

location

location of the error

label

label of the affected DIMM(s)

grain

minimum granularity for an error report, in bytes

error_count

number of errors of the same type

type

severity of the error (CE/UE/Fatal)

top_layer

top layer of the error (layer[0])

mid_layer

middle layer of the error (layer[1])

low_layer

low layer of the error (layer[2])

page_frame_number

page where the error happened

offset_in_page

page offset

syndrome

syndrome of the error (or 0 if unknown or ifthe syndrome is not applicable)

msg

error message

other_detail

other driver-specific detail about the error

struct dimm_info *edac_get_dimm_by_index(struct mem_ctl_info * mci, int index)¶

Get DIMM info atindex from a memory controller

Parameters

structmem_ctl_info*mci

MC descriptor struct mem_ctl_info

intindex

index in the memory controller’s DIMM array

Description

Returns a struct dimm_info * or NULL on failure.

struct dimm_info *edac_get_dimm(struct mem_ctl_info * mci, int layer0, int layer1, int layer2)¶

Get DIMM info from a memory controller given by [layer0,layer1,layer2] position

Parameters

structmem_ctl_info*mci

MC descriptor struct mem_ctl_info

intlayer0

layer0 position

intlayer1

layer1 position. Unused if n_layers < 2

intlayer2

layer2 position. Unused if n_layers < 3

Description

For 1 layer, this function returns “dimms[layer0]”;

For 2 layers, this function is similar to allocating a two-dimensionalarray and returning “dimms[layer0][layer1]”;

For 3 layers, this function is similar to allocating a tri-dimensionalarray and returning “dimms[layer0][layer1][layer2]”;

struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, unsigned int n_layers, structedac_mc_layer * layers, unsigned int sz_pvt)¶

Allocate and partially fill a structmem_ctl_info.

Parameters

unsignedintmc_num

Memory controller number

unsignedintn_layers

Number of MC hierarchy layers

structedac_mc_layer*layers

Describes each layer as seen by the Memory Controller

unsignedintsz_pvt

size of private storage needed

Description

Everything is kmalloc’ed as one big chunk - more efficient.Only can be used if all structures have the same lifetime - otherwiseyou have to allocate and initialize your own structures.

Useedac_mc_free() to free mc structures allocated by this function.

Return

On success, return a pointer to struct mem_ctl_info pointer;NULL otherwise

const char *edac_get_owner(void)¶

Return the owner’s mod_name of EDAC MC

Parameters

void

no arguments

Return

Pointer to mod_name string when EDAC MC is owned. NULL otherwise.

voidedac_mc_free(struct mem_ctl_info * mci)¶

Frees a previously allocatedmci structure

Parameters

structmem_ctl_info*mci

pointer to a struct mem_ctl_info structure

booledac_has_mcs(void)¶

Check if any MCs have been allocated.

Parameters

void

no arguments

Return

True if MC instances have been registered successfully.False otherwise.

struct mem_ctl_info *edac_mc_find(int idx)¶

Search for a mem_ctl_info structure whose index isidx.

Parameters

intidx

index to be seek

Description

If found, return a pointer to the structure.Else return NULL.

struct mem_ctl_info *find_mci_by_dev(structdevice * dev)¶

Scan list of controllers looking for the one that manages thedev device.

Parameters

structdevice*dev

pointer to a struct device related with the MCI

Return

on success, returns a pointer to structmem_ctl_info;NULL otherwise.

struct mem_ctl_info *edac_mc_del_mc(structdevice * dev)¶

Remove sysfs entries for mci structure associated withdev and remove mci structure from global list.

Parameters

structdevice*dev

Pointer to structdevice representing mci structure to remove.

Return

pointer to removed mci structure, orNULL if device not found.

intedac_mc_find_csrow_by_page(struct mem_ctl_info * mci, unsigned long page)¶

Ancillary routine to identify what csrow contains a memory page.

Parameters

structmem_ctl_info*mci

pointer to a struct mem_ctl_info structure

unsignedlongpage

memory page to find

Return

on success, returns the csrow. -1 if not found.

voidedac_raw_mc_handle_error(structedac_raw_error_desc * e)¶

Reports a memory event to userspace without doing anything to discover the error location.

Parameters

structedac_raw_error_desc*e

error description

Description

This raw function is used internally byedac_mc_handle_error(). It shouldonly be called directly when the hardware error come directly from BIOS,like in the case of APEI GHES driver.

voidedac_mc_handle_error(const enumhw_event_mc_err_type type, struct mem_ctl_info * mci, const u16 error_count, const unsigned long page_frame_number, const unsigned long offset_in_page, const unsigned long syndrome, const int top_layer, const int mid_layer, const int low_layer, const char * msg, const char * other_detail)¶

Reports a memory event to userspace.

Parameters

constenumhw_event_mc_err_typetype

severity of the error (CE/UE/Fatal)

structmem_ctl_info*mci

a struct mem_ctl_info pointer

constu16error_count

Number of errors of the same type

constunsignedlongpage_frame_number

mem page where the error occurred

constunsignedlongoffset_in_page

offset of the error inside the page

constunsignedlongsyndrome

ECC syndrome

constinttop_layer

Memory layer[0] position

constintmid_layer

Memory layer[1] position

constintlow_layer

Memory layer[2] position

constchar*msg

Message meaningful to the end users thatexplains the event

constchar*other_detail

Technical details about the event thatmay help hardware manufacturers andEDAC developers to analyse the event

PCI Controllers¶

The EDAC subsystem provides a mechanism to handle PCI controllers by callingtheedac_pci_alloc_ctl_info(). It will use the structedac_pci_ctl_info to describe the PCI controllers.

struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt, const char * edac_pci_name)¶

Parameters

unsignedintsz_pvt

size of the private info at structedac_pci_ctl_info

constchar*edac_pci_name

name of the PCI device

Description

The alloc() function for the ‘edac_pci’ control infostructure.

The chip driver will allocate one of these for eachedac_pci it is going to control/register with the EDAC CORE.

Return

a pointer to structedac_pci_ctl_info on success;NULL otherwise.

voidedac_pci_free_ctl_info(struct edac_pci_ctl_info * pci)¶

Parameters

structedac_pci_ctl_info*pci

pointer to structedac_pci_ctl_info

Description

Last action on the pci control structure.

Calls the remove sysfs information, which will unregisterthis control struct’s kobj. When that kobj’s ref countgoes to zero, its release function will be call and thenkfree() the memory.

intedac_pci_alloc_index(void)¶

Parameters

void

no arguments

Return

allocated index number

intedac_pci_add_device(struct edac_pci_ctl_info * pci, int edac_idx)¶

Parameters

structedac_pci_ctl_info*pci

pointer to the edac_device structure to be added to the list

intedac_idx

A unique numeric identifier to be assigned to the‘edac_pci’ structure.

Description

edac_pci global list and create sysfs entries associated withedac_pci structure.

Return

0 on Success, or an error code on failure

struct edac_pci_ctl_info *edac_pci_del_device(structdevice * dev)¶

Parameters

structdevice*dev

Pointer to ‘struct device’ representing edac_pci structureto remove

Description

Remove sysfs entries for specified edac_pci structure andthen remove edac_pci structure from global list

Return

Pointer to removed edac_pci structure,orNULL if device not found

struct edac_pci_ctl_info *edac_pci_create_generic_ctl(structdevice * dev, const char * mod_name)¶

Parameters

structdevice*dev

pointer to structdevice;

constchar*mod_name

name of the PCI device

Description

A generic constructor for a PCI parity polling deviceSome systems have more than one domain of PCI busses.For systems with one domain, then this API willprovide for a generic poller.

This routine calls theedac_pci_alloc_ctl_info() forthe generic device, with default values

Return

Pointer to structedac_pci_ctl_info on success,NULL on

failure.

voidedac_pci_release_generic_ctl(struct edac_pci_ctl_info * pci)¶

Parameters

structedac_pci_ctl_info*pci

pointer to structedac_pci_ctl_info

Description

The release function of a generic EDAC PCI polling device

intedac_pci_create_sysfs(struct edac_pci_ctl_info * pci)¶

Parameters

structedac_pci_ctl_info*pci

pointer to structedac_pci_ctl_info

Description

Create the controls/attributes for the specified EDAC PCI device

voidedac_pci_remove_sysfs(struct edac_pci_ctl_info * pci)¶

Parameters

structedac_pci_ctl_info*pci

pointer to structedac_pci_ctl_info

Description

remove the controls and attributes for this EDAC PCI device

EDAC Blocks¶

The EDAC subsystem also provides a generic mechanism to report errors onother parts of the hardware viaedac_device_alloc_ctl_info() function.

The structuresedac_dev_sysfs_block_attribute,edac_device_block,edac_device_instance andedac_device_ctl_info provide a generic or abstract ‘edac_device’representation at sysfs.

This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory orPCI, like:

• CPU caches (L1 and L2)
• DMA engines
• Core CPU switches
• Fabric switch units
• PCIe interface controllers
• other EDAC/ECC type devices that can be monitored forerrors, etc.

It allows for a 2 level set of hierarchy.

For example, a cache could be composed of L1, L2 and L3 levels of cache.Each CPU core would have its own L1 cache, while sharing L2 and maybe L3caches. On such case, those can be represented via the following sysfsnodes:

/sys/devices/system/edac/..pci/            <existing pci directory (if available)>mc/             <existing memory device directory>cpu/cpu0/..     <L1 and L2 block directory>        /L1-cache/ce_count                 /ue_count        /L2-cache/ce_count                 /ue_countcpu/cpu1/..     <L1 and L2 block directory>        /L1-cache/ce_count                 /ue_count        /L2-cache/ce_count                 /ue_count...the L1 and L2 directories would be "edac_device_block's"

intedac_device_add_device(struct edac_device_ctl_info * edac_dev)¶

Parameters

structedac_device_ctl_info*edac_dev

pointer to edac_device structure to be added to the list‘edac_device’ structure.

Description

edac_device global list and create sysfs entries associated withedac_device structure.

Return

0 on Success, or an error code on failure

struct edac_device_ctl_info *edac_device_del_device(structdevice * dev)¶

Parameters

structdevice*dev

Pointer to structdevice representing the edac devicestructure to remove.

Description

Remove sysfs entries for specified edac_device structure andthen remove edac_device structure from global list

Return

Pointer to removed edac_device structure,orNULL if device not found.

voidedac_device_handle_ce_count(struct edac_device_ctl_info * edac_dev, unsigned int count, int inst_nr, int block_nr, const char * msg)¶

Parameters

structedac_device_ctl_info*edac_dev

pointer to structedac_device_ctl_info

unsignedintcount

Number of errors to log.

intinst_nr

number of the instance where the CE error happened

intblock_nr

number of the block where the CE error happened

constchar*msg

message to be printed

voidedac_device_handle_ue_count(struct edac_device_ctl_info * edac_dev, unsigned int count, int inst_nr, int block_nr, const char * msg)¶

Parameters

structedac_device_ctl_info*edac_dev

pointer to structedac_device_ctl_info

unsignedintcount

Number of errors to log.

intinst_nr

number of the instance where the CE error happened

intblock_nr

number of the block where the CE error happened

constchar*msg

message to be printed

voidedac_device_handle_ce(struct edac_device_ctl_info * edac_dev, int inst_nr, int block_nr, const char * msg)¶

Parameters

structedac_device_ctl_info*edac_dev

pointer to structedac_device_ctl_info

intinst_nr

number of the instance where the CE error happened

intblock_nr

number of the block where the CE error happened

constchar*msg

message to be printed

voidedac_device_handle_ue(struct edac_device_ctl_info * edac_dev, int inst_nr, int block_nr, const char * msg)¶

Parameters

structedac_device_ctl_info*edac_dev

pointer to structedac_device_ctl_info

intinst_nr

number of the instance where the UE error happened

intblock_nr

number of the block where the UE error happened

constchar*msg

message to be printed

intedac_device_alloc_index(void)¶

Parameters

void

no arguments

Return

allocated index number