PHY Abstraction Layer

Purpose

Most network devices consist of set of registers which provide an interfaceto a MAC layer, which communicates with the physical connection through aPHY. The PHY concerns itself with negotiating link parameters with the linkpartner on the other side of the network connection (typically, an ethernetcable), and provides a register interface to allow drivers to determine whatsettings were chosen, and to configure what settings are allowed.

While these devices are distinct from the network devices, and conform to astandard layout for the registers, it has been common practice to integratethe PHY management code with the network driver. This has resulted in largeamounts of redundant code. Also, on embedded systems with multiple (andsometimes quite different) ethernet controllers connected to the samemanagement bus, it is difficult to ensure safe use of the bus.

Since the PHYs are devices, and the management busses through which they areaccessed are, in fact, busses, the PHY Abstraction Layer treats them as such.In doing so, it has these goals:

  1. Increase code-reuse
  2. Increase overall code-maintainability
  3. Speed development time for new network drivers, and for new systems

Basically, this layer is meant to provide an interface to PHY devices whichallows network driver writers to write as little code as possible, whilestill providing a full feature set.

The MDIO bus

Most network devices are connected to a PHY by means of a management bus.Different devices use different busses (though some share common interfaces).In order to take advantage of the PAL, each bus interface needs to beregistered as a distinct device.

  1. read and write functions must be implemented. Their prototypes are:

    int write(struct mii_bus *bus, int mii_id, int regnum, u16 value);int read(struct mii_bus *bus, int mii_id, int regnum);

    mii_id is the address on the bus for the PHY, and regnum is the registernumber. These functions are guaranteed not to be called from interrupttime, so it is safe for them to block, waiting for an interrupt to signalthe operation is complete

  2. A reset function is optional. This is used to return the bus to aninitialized state.

  3. A probe function is needed. This function should set up anything the busdriver needs, setup the mii_bus structure, and register with the PAL usingmdiobus_register. Similarly, there’s a remove function to undo all ofthat (use mdiobus_unregister).

  4. Like any driver, the device_driver structure must be configured, and initexit functions are used to register the driver.

  5. The bus must also be declared somewhere as a device, and registered.

As an example for how one driver implemented an mdio bus driver, seedrivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS filefor one of the users. (e.g. “git grep fsl,.*-mdio arch/powerpc/boot/dts/”)

(RG)MII/electrical interface considerations

The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pinelectrical signal interface using a synchronous 125Mhz clock signal and severaldata lines. Due to this design decision, a 1.5ns to 2ns delay must be addedbetween the clock line (RXC or TXC) and the data lines to let the PHY (clocksink) have a large enough setup and hold time to sample the data lines correctly. ThePHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to letthe PHY driver and optionally the MAC driver, implement the required delay. Thevalues of phy_interface_t must be understood from the perspective of the PHYdevice itself, leading to the following:

  • PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting anyinternal delay by itself, it assumes that either the Ethernet MAC (if capableor the PCB traces) insert the correct 1.5-2ns delay
  • PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delayfor the transmit data lines (TXD[3:0]) processed by the PHY device
  • PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delayfor the receive data lines (RXD[3:0]) processed by the PHY device
  • PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays forboth transmit AND receive data lines from/to the PHY device

Whenever possible, use the PHY side RGMII delay for these reasons:

  • PHY devices may offer sub-nanosecond granularity in how they allow areceiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Suchprecision may be required to account for differences in PCB trace lengths
  • PHY devices are typically qualified for a large range of applications(industrial, medical, automotive…), and they provide a constant andreliable delay across temperature/pressure/voltage ranges
  • PHY device drivers in PHYLIB being reusable by nature, being able toconfigure correctly a specified delay enables more designs with similar delayrequirements to be operate correctly

For cases where the PHY is not capable of providing this delay, but theEthernet MAC driver is capable of doing so, the correct phy_interface_t valueshould be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should beconfigured correctly in order to provide the required transmit and/or receiveside delay from the perspective of the PHY device. Conversely, if the EthernetMAC driver looks at the phy_interface_t value, for any other mode butPHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays aredisabled.

In case neither the Ethernet MAC, nor the PHY are capable of providing therequired delays, as defined per the RGMII standard, several options may beavailable:

  • Some SoCs may offer a pin pad/mux/controller capable of configuring a givenset of pins’strength, delays, and voltage; and it may be a suitableoption to insert the expected 2ns RGMII delay.
  • Modifying the PCB design to include a fixed delay (e.g: using a specificallydesigned serpentine), which may not require software configuration at all.

Common problems with RGMII delay mismatch

When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, thiswill most likely result in the clock and data line signals to be unstable whenthe PHY or MAC take a snapshot of these signals to translate them into logical1 or 0 states and reconstruct the data being transmitted/received. Typicalsymptoms include:

  • Transmission/reception partially works, and there is frequent or occasionalpacket loss observed
  • Ethernet MAC may report some or all packets ingressing with a FCS/CRC error,or just discard them all
  • Switching to lower speeds such as 10/100Mbits/sec makes the problem go away(since there is enough setup/hold time in that case)

Connecting to a PHY

Sometime during startup, the network driver needs to establish a connectionbetween the PHY device, and the network device. At this time, the PHY’s busand drivers need to all have been loaded, so it is ready for the connection.At this point, there are several ways to connect to the PHY:

  1. The PAL handles everything, and only calls the network driver whenthe link state changes, so it can react.
  2. The PAL handles everything except interrupts (usually because thecontroller has the interrupt registers).
  3. The PAL handles everything, but checks in with the driver every second,allowing the network driver to react first to any changes before the PALdoes.
  4. The PAL serves only as a library of functions, with the network devicemanually calling functions to update status, and configure the PHY

Letting the PHY Abstraction Layer do Everything

If you choose option 1 (The hope is that every driver can, but to still beuseful to drivers that can’t), connecting to the PHY is simple:

First, you need a function to react to changes in the link state. Thisfunction follows this protocol:

static void adjust_link(struct net_device *dev);

Next, you need to know the device name of the PHY connected to this device.The name will look something like, “0:00”, where the first number is thebus id, and the second is the PHY’s address on that bus. Typically,the bus is responsible for making its ID unique.

Now, to connect, just call this function:

phydev = phy_connect(dev, phy_name, &adjust_link, interface);

phydev is a pointer to the phy_device structure which represents the PHY.If phy_connect is successful, it will return the pointer. dev, here, is thepointer to your net_device. Once done, this function will have started thePHY’s software state machine, and registered for the PHY’s interrupt, if ithas one. The phydev structure will be populated with information about thecurrent state, though the PHY will not yet be truly operational at thispoint.

PHY-specific flags should be set in phydev->dev_flags prior to the calltophy_connect() such that the underlying PHY driver can check for flagsand perform specific operations based on them.This is useful if the system has put hardware restrictions onthe PHY/controller, of which the PHY needs to be aware.

interface is a u32 which specifies the connection type usedbetween the controller and the PHY. Examples are GMII, MII,RGMII, and SGMII. See “PHY interface mode” below. For a fulllist, see include/linux/phy.h

Now just make sure that phydev->supported and phydev->advertising have anyvalues pruned from them which don’t make sense for your controller (a 10/100controller may be connected to a gigabit capable PHY, so you would need tomask off SUPPORTED_1000baseT*). See include/linux/ethtool.h for definitionsfor these bitfields. Note that you should not SET any bits, except theSUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may getput into an unsupported state.

Lastly, once the controller is ready to handle network traffic, you callphy_start(phydev). This tells the PAL that you are ready, and configures thePHY to connect to the network. If the MAC interrupt of your network driveralso handles PHY status changes, just set phydev->irq to PHY_IGNORE_INTERRUPTbefore you call phy_start and usephy_mac_interrupt() from the networkdriver. If you don’t want to use interrupts, set phydev->irq to PHY_POLL.phy_start() enables the PHY interrupts (if applicable) and starts thephylib state machine.

When you want to disconnect from the network (even if just briefly), you callphy_stop(phydev). This function also stops the phylib state machine anddisables PHY interrupts.

PHY interface modes

The PHY interface mode supplied in thephy_connect() family of functionsdefines the initial operating mode of the PHY interface. This is notguaranteed to remain constant; there are PHYs which dynamically changetheir interface mode without software interaction depending on thenegotiation results.

Some of the interface modes are described below:

PHY_INTERFACE_MODE_1000BASEX
This defines the 1000BASE-X single-lane serdes link as defined by the802.3 standard section 36. The link operates at a fixed bit rate of1.25Gbaud using a 10B/8B encoding scheme, resulting in an underlyingdata rate of 1Gbps. Embedded in the data stream is a 16-bit controlword which is used to negotiate the duplex and pause modes with theremote end. This does not include “up-clocked” variants such as 2.5Gbpsspeeds (see below.)
PHY_INTERFACE_MODE_2500BASEX
This defines a variant of 1000BASE-X which is clocked 2.5 times faster,than the 802.3 standard giving a fixed bit rate of 3.125Gbaud.
PHY_INTERFACE_MODE_SGMII

This is used for Cisco SGMII, which is a modification of 1000BASE-Xas defined by the 802.3 standard. The SGMII link consists of a singleserdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8Bencoding. The underlying data rate is 1Gbps, with the slower speeds of100Mbps and 10Mbps being achieved through replication of each data symbol.The 802.3 control word is re-purposed to send the negotiated speed andduplex information from to the MAC, and for the MAC to acknowledgereceipt. This does not include “up-clocked” variants such as 2.5Gbpsspeeds.

Note: mismatched SGMII vs 1000BASE-X configuration on a link cansuccessfully pass data in some circumstances, but the 16-bit controlword will not be correctly interpreted, which may cause mismatches induplex, pause or other settings. This is dependent on the MAC and/orPHY behaviour.

PHY_INTERFACE_MODE_10GBASER

This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used withvarious different mediums. Please refer to the IEEE standard for adefinition of this.

Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.XFI and SFI permit multiple protocols over a single SERDES lane, andalso defines the electrical characteristics of the signals with a hostcompliance board plugged into the host XFP/SFP connector. Therefore,XFI and SFI are not PHY interface types in their own right.

PHY_INTERFACE_MODE_10GKR

This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73autonegotiation. Please refer to the IEEE standard for furtherinformation.

Note: due to legacy usage, some 10GBASE-R usage incorrectly makesuse of this definition.

Pause frames / flow control

The PHY does not participate directly in flow control/pause frames except bymaking sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set inMII_ADVERTISE to indicate towards the link partner that the Ethernet MACcontroller supports such a thing. Since flow control/pause frames generationinvolves the Ethernet MAC driver, it is recommended that this driver takes careof properly indicating advertisement and support for such features by settingthe SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be doneeither before or afterphy_connect() and/or as a result of implementing theethtool::set_pauseparam feature.

Keeping Close Tabs on the PAL

It is possible that the PAL’s built-in state machine needs a little help tokeep your network device and the PHY properly in sync. If so, you canregister a helper function when connecting to the PHY, which will be calledevery second before the state machine reacts to any changes. To do this, youneed to manually callphy_attach() andphy_prepare_link(), and then callphy_start_machine() with the second argument set to point to your specialhandler.

Currently there are no examples of how to use this functionality, and testingon it has been limited because the author does not have any drivers which useit (they all use option 1). So Caveat Emptor.

Doing it all yourself

There’s a remote chance that the PAL’s built-in state machine cannot trackthe complex interactions between the PHY and your network device. If this isso, you can simply callphy_attach(), and not call phy_start_machine orphy_prepare_link(). This will mean that phydev->state is entirely yours tohandle (phy_start and phy_stop toggle between some of the states, so youmight need to avoid them).

An effort has been made to make sure that useful functionality can beaccessed without the state-machine running, and most of these functions aredescended from functions which did not interact with a complex state-machine.However, again, no effort has been made so far to test running without thestate machine, so tryer beware.

Here is a brief rundown of the functions:

int phy_read(struct phy_device *phydev, u16 regnum);int phy_write(struct phy_device *phydev, u16 regnum, u16 val);

Simple read/write primitives. They invoke the bus’s read/write functionpointers.

void phy_print_status(struct phy_device *phydev);

A convenience function to print out the PHY status neatly.

void phy_request_interrupt(struct phy_device *phydev);

Requests the IRQ for the PHY interrupts.

struct phy_device * phy_attach(struct net_device *dev, const char *phy_id,                               phy_interface_t interface);

Attaches a network device to a particular PHY, binding the PHY to a genericdriver if none was found during bus initialization.

int phy_start_aneg(struct phy_device *phydev);

Using variables inside the phydev structure, either configures advertisingand resets autonegotiation, or disables autonegotiation, and configuresforced settings.

static inline int phy_read_status(struct phy_device *phydev);

Fills the phydev structure with up-to-date information about the currentsettings in the PHY.

int phy_ethtool_ksettings_set(struct phy_device *phydev,                              const struct ethtool_link_ksettings *cmd);

Ethtool convenience functions.

int phy_mii_ioctl(struct phy_device *phydev,                  struct mii_ioctl_data *mii_data, int cmd);

The MII ioctl. Note that this function will completely screw up the statemachine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best touse this only to write registers which are not standard, and don’t set offa renegotiation.

PHY Device Drivers

With the PHY Abstraction Layer, adding support for new PHYs isquite easy. In some cases, no work is required at all! However,many PHYs require a little hand-holding to get up-and-running.

Generic PHY driver

If the desired PHY doesn’t have any errata, quirks, or specialfeatures you want to support, then it may be best to not addsupport, and let the PHY Abstraction Layer’s Generic PHY Driverdo all of the work.

Writing a PHY driver

If you do need to write a PHY driver, the first thing to do ismake sure it can be matched with an appropriate PHY device.This is done during bus initialization by reading the device’sUID (stored in registers 2 and 3), then comparing it to eachdriver’s phy_id field by ANDing it with each driver’sphy_id_mask field. Also, it needs a name. Here’s an example:

static struct phy_driver dm9161_driver = {      .phy_id         = 0x0181b880,      .name           = "Davicom DM9161E",      .phy_id_mask    = 0x0ffffff0,      ...}

Next, you need to specify what features (speed, duplex, autoneg,etc) your PHY device and driver support. Most PHYs supportPHY_BASIC_FEATURES, but you can look in include/mii.h for otherfeatures.

Each driver consists of a number of function pointers, documentedin include/linux/phy.h under the phy_driver structure.

Of these, only config_aneg and read_status are required to beassigned by the driver code. The rest are optional. Also, it ispreferred to use the generic phy driver’s versions of these twofunctions if at all possible: genphy_read_status andgenphy_config_aneg. If this is not possible, it is likely thatyou only need to perform some actions before and after invokingthese functions, and so your functions will wrap the genericones.

Feel free to look at the Marvell, Cicada, and Davicom drivers indrivers/net/phy/ for examples (the lxt and qsemi drivers havenot been tested as of this writing).

The PHY’s MMD register accesses are handled by the PAL frameworkby default, but can be overridden by a specific PHY driver ifrequired. This could be the case if a PHY was released formanufacturing before the MMD PHY register definitions werestandardized by the IEEE. Most modern PHYs will be able to usethe generic PAL framework for accessing the PHY’s MMD registers.An example of such usage is for Energy Efficient Ethernet support,implemented in the PAL. This support uses the PAL to access MMDregisters for EEE query and configuration if the PHY supportsthe IEEE standard access mechanisms, or can use the PHY’s specificaccess interfaces if overridden by the specific PHY driver. Seethe Micrel driver in drivers/net/phy/ for an example of how thiscan be implemented.

Board Fixups

Sometimes the specific interaction between the platform and the PHY requiresspecial handling. For instance, to change where the PHY’s clock input is,or to add a delay to account for latency issues in the data path. In orderto support such contingencies, the PHY Layer allows platform code to registerfixups to be run when the PHY is brought up (or subsequently reset).

When the PHY Layer brings up a PHY it checks to see if there are any fixupsregistered for it, matching based on UID (contained in the PHY device’s phy_idfield) and the bus identifier (contained in phydev->dev.bus_id). Both mustmatch, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided aswildcards for the bus ID and UID, respectively.

When a match is found, the PHY layer will invoke the run function associatedwith the fixup. This function is passed a pointer to the phy_device ofinterest. It should therefore only operate on that PHY.

The platform code can either register the fixup usingphy_register_fixup():

int phy_register_fixup(const char *phy_id,        u32 phy_uid, u32 phy_uid_mask,        int (*run)(struct phy_device *));

Or using one of the two stubs, phy_register_fixup_for_uid() andphy_register_fixup_for_id():

int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,               int (*run)(struct phy_device *));int phy_register_fixup_for_id(const char *phy_id,               int (*run)(struct phy_device *));

The stubs set one of the two matching criteria, and set the other one tomatch anything.

Whenphy_register_fixup() or *_for_uid()/*_for_id() is called at module loadtime, the module needs to unregister the fixup and free allocated memory whenit’s unloaded.

Call one of following function before unloading module:

int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask);int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);int phy_register_fixup_for_id(const char *phy_id);