Reliability, Availability and Serviceability¶

RAS concepts¶

Reliability, Availability and Serviceability (RAS) is a concept used onservers meant to measure their robustness.

Reliability

is the probability that a system will produce correct outputs.

Generally measured as Mean Time Between Failures (MTBF)
Enhanced by features that help to avoid, detect and repair hardware faults

Availability

is the probability that a system is operational at a given time

Generally measured as a percentage of downtime per a period of time
Often uses mechanisms to detect and correct hardware faults inruntime;

Serviceability (or maintainability)

is the simplicity and speed with which a system can be repaired ormaintained

Generally measured on Mean Time Between Repair (MTBR)

Improving RAS¶

In order to reduce systems downtime, a system should be capable of detectinghardware errors, and, when possible correcting them in runtime. It shouldalso provide mechanisms to detect hardware degradation, in order to warnthe system administrator to take the action of replacing a component beforeit causes data loss or system downtime.

Among the monitoring measures, the most usual ones include:

CPU – detect errors at instruction execution and at L1/L2/L3 caches;
Memory – add error correction logic (ECC) to detect and correct errors;
I/O – add CRC checksums for transferred data;
Storage – RAID, journal file systems, checksums,Self-Monitoring, Analysis and Reporting Technology (SMART).

By monitoring the number of occurrences of error detections, it is possibleto identify if the probability of hardware errors is increasing, and, on suchcase, do a preventive maintenance to replace a degraded component whilethose errors are correctable.

Types of errors¶

Most mechanisms used on modern systems use technologies like HammingCodes that allow error correction when the number of errors on a bit packetis below a threshold. If the number of errors is above, those mechanismscan indicate with a high degree of confidence that an error happened, butthey can’t correct.

Also, sometimes an error occur on a component that it is not used. Forexample, a part of the memory that it is not currently allocated.

That defines some categories of errors:

Correctable Error (CE) - the error detection mechanism detected andcorrected the error. Such errors are usually not fatal, although someKernel mechanisms allow the system administrator to consider them as fatal.
Uncorrected Error (UE) - the amount of errors happened above the errorcorrection threshold, and the system was unable to auto-correct.
Fatal Error - when an UE error happens on a critical component of thesystem (for example, a piece of the Kernel got corrupted by an UE), theonly reliable way to avoid data corruption is to hang or reboot the machine.
Non-fatal Error - when an UE error happens on an unused component,like a CPU in power down state or an unused memory bank, the system maystill run, eventually replacing the affected hardware by a hot spare,if available.
Also, when an error happens on a userspace process, it is also possible tokill such process and let userspace restart it.

The mechanism for handling non-fatal errors is usually complex and mayrequire the help of some userspace application, in order to apply thepolicy desired by the system administrator.

Identifying a bad hardware component¶

Just detecting a hardware flaw is usually not enough, as the system needsto pinpoint to the minimal replaceable unit (MRU) that should be exchangedto make the hardware reliable again.

So, it requires not only error logging facilities, but also mechanisms thatwill translate the error message to the silkscreen or component label forthe MRU.

Typically, it is very complex for memory, as modern CPUs interlace memoryfrom different memory modules, in order to provide a better performance. TheDMI BIOS usually have a list of memory module labels, with can be obtainedusing thedmidecode tool. For example, on a desktop machine, it shows:

Memory Device        Total Width: 64 bits        Data Width: 64 bits        Size: 16384 MB        Form Factor: SODIMM        Set: None        Locator: ChannelA-DIMM0        Bank Locator: BANK 0        Type: DDR4        Type Detail: Synchronous        Speed: 2133 MHz        Rank: 2        Configured Clock Speed: 2133 MHz

On the above example, a DDR4 SO-DIMM memory module is located at thesystem’s memory labeled as “BANK 0”, as given by thebank locator field.Please notice that, on such system, thetotal width is equal to thedata width. It means that such memory module doesn’t have errordetection/correction mechanisms.

Unfortunately, not all systems use the same field to specify the memorybank. On this example, from an older server,dmidecode shows:

Memory Device        Array Handle: 0x1000        Error Information Handle: Not Provided        Total Width: 72 bits        Data Width: 64 bits        Size: 8192 MB        Form Factor: DIMM        Set: 1        Locator: DIMM_A1        Bank Locator: Not Specified        Type: DDR3        Type Detail: Synchronous Registered (Buffered)        Speed: 1600 MHz        Rank: 2        Configured Clock Speed: 1600 MHz

There, the DDR3 RDIMM memory module is located at the system’s memory labeledas “DIMM_A1”, as given by thelocator field. Please notice that thismemory module has 64 bits ofdata width and 72 bits oftotal width. So,it has 8 extra bits to be used by error detection and correction mechanisms.Such kind of memory is called Error-correcting code memory (ECC memory).

To make things even worse, it is not uncommon that systems with differentlabels on their system’s board to use exactly the same BIOS, meaning thatthe labels provided by the BIOS won’t match the real ones.

ECC memory¶

As mentioned in the previous section, ECC memory has extra bits to beused for error correction. In the above example, a memory module has64 bits ofdata width, and 72 bits oftotal width. The extra 8bits which are used for the error detection and correction mechanismsare referred to as thesyndrome[1][2].

So, when the cpu requests the memory controller to write a word withdata width, the memory controller calculates thesyndrome in real time,using Hamming code, or some other error correction code, like SECDED+,producing a code withtotal width size. Such code is then writtenon the memory modules.

At read, thetotal width bits code is converted back, using the sameECC code used on write, producing a word withdata width and asyndrome.The word withdata width is sent to the CPU, even when errors happen.

The memory controller also looks at thesyndrome in order to check ifthere was an error, and if the ECC code was able to fix such error.If the error was corrected, a Corrected Error (CE) happened. If not, anUncorrected Error (UE) happened.

The information about the CE/UE errors is stored on some special registersat the memory controller and can be accessed by reading such registers,either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64bit CPUs, such errors can also be retrieved via the Machine CheckArchitecture (MCA)[3].

[1]

Please notice that several memory controllers allow operation on amode called “Lock-Step”, where it groups two memory modules together,doing 128-bit reads/writes. That gives 16 bits for error correction, withsignificantly improves the error correction mechanism, at the expensethat, when an error happens, there’s no way to know what memory module isto blame. So, it has to blame both memory modules.

[2]

Some memory controllers also allow using memory in mirror mode.On such mode, the same data is written to two memory modules. At read,the system checks both memory modules, in order to check if both provideidentical data. On such configuration, when an error happens, there’s noway to know what memory module is to blame. So, it has to blame bothmemory modules (or 4 memory modules, if the system is also on Lock-stepmode).

[3]	For more details about the Machine Check Architecture (MCA),please read Documentation/x86/x86_64/machinecheck.rst at the Kernel tree.

EDAC - Error Detection And Correction¶

Note

“bluesmoke” was the name for this device driver subsystem when itwas “out-of-tree” and maintained athttp://bluesmoke.sourceforge.net.That site is mostly archaic now and can be used only for historicalpurposes.

When the subsystem was pushed upstream for the first time, onKernel 2.6.16, it was renamed toEDAC.

Purpose¶

Theedac kernel module’s goal is to detect and report hardware errorsthat occur within the computer system running under linux.

Memory¶

Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are theprimary errors being harvested. These types of errors are harvested bytheedac_mc device.

Detecting CE events, then harvesting those events and reporting them,can but must not necessarily be a predictor of future UE events. WithCE events only, the system can and will continue to operate as no datahas been damaged yet.

However, preventive maintenance and proactive part replacement of memorymodules exhibiting CEs can reduce the likelihood of the dreaded UE eventsand system panics.

Other hardware elements¶

A new feature for EDAC, theedac_device class of device, was added inthe 2.6.23 version of the kernel.

This new device type allows for non-memory type of ECC hardware detectorsto have their states harvested and presented to userspace via the sysfsinterface.

Some architectures have ECC detectors for L1, L2 and L3 caches,along with DMA engines, fabric switches, main data path switches,interconnections, and various other hardware data paths. If the hardwarereports it, then a edac_device device probably can be constructed toharvest and present that to userspace.

PCI bus scanning¶

In addition, PCI devices are scanned for PCI Bus Parity and SERR Errorsin order to determine if errors are occurring during data transfers.

The presence of PCI Parity errors must be examined with a grain of salt.There are several add-in adapters that donot follow the PCI specificationwith regards to Parity generation and reporting. The specification saysthe vendor should tie the parity status bits to 0 if they do not intendto generate parity. Some vendors do not do this, and thus the parity bitcan “float” giving false positives.

There is a PCI device attribute located in sysfs that is checked bythe EDAC PCI scanning code. If that attribute is set, PCI parity/errorscanning is skipped for that device. The attribute is:

broken_parity_status

and is located in/sys/devices/pci<XXX>/0000:XX:YY.Z directories forPCI devices.

Versioning¶

EDAC is composed of a “core” module (edac_core.ko) and several MemoryController (MC) driver modules. On a given system, the CORE is loadedand one MC driver will be loaded. Both the CORE and the MC driver (oredac_device driver) have individual versions that reflect currentrelease level of their respective modules.

Thus, to “report” on what version a system is running, one must reportboth the CORE’s and the MC driver’s versions.

Loading¶

Ifedac was statically linked with the kernel then no loadingis necessary. Ifedac was built as modules then simply modprobetheedac pieces that you need. You should be able to modprobehardware-specific modules and have the dependencies load the necessarycore modules.

Example:

$ modprobe amd76x_edac

loads both theamd76x_edac.ko memory controller module and theedac_mc.ko core module.

Sysfs interface¶

EDAC presents asysfs interface for control and reporting purposes. Itlives in the /sys/devices/system/edac directory.

Within this directory there currently reside 2 components:

mc memory controller(s) system
pci PCI control and status system

Memory Controller (mc) Model¶

Eachmc device controls a set of memory modules[4]. These modulesare laid out in a Chip-Select Row (csrowX) and Channel table (chX).There can be multiple csrows and multiple channels.

[4]

Nowadays, the term DIMM (Dual In-line Memory Module) is widelyused to refer to a memory module, although there are other memorypackaging alternatives, like SO-DIMM, SIMM, etc. The UEFIspecification (Version 2.7) defines a memory module in the CommonPlatform Error Record (CPER) section to be an SMBIOS Memory Device(Type 17). Along this document, and inside the EDAC subsystem, the term“dimm” is used for all memory modules, even when they use adifferent kind of packaging.

Memory controllers allow for several csrows, with 8 csrows being atypical value. Yet, the actual number of csrows depends on the layout ofa given motherboard, memory controller and memory module characteristics.

Dual channels allow for dual data length (e. g. 128 bits, on 64 bit systems)data transfers to/from the CPU from/to memory. Some newer chipsets allowfor more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memorycontrollers. The following example will assume 2 channels:

CS Rows Channels
ch0 ch1
DIMM_A0 DIMM_B0
csrow0 rank0 rank0
csrow1 rank1 rank1
DIMM_A1 DIMM_B1
csrow2 rank0 rank0
csrow3 rank1 rank1

CS Rows	Channels
	DIMM_A0	DIMM_B0
`csrow0`	rank0	rank0
`csrow1`	rank1	rank1
	DIMM_A1	DIMM_B1
`csrow2`	rank0	rank0
`csrow3`	rank1	rank1

In the above example, there are 4 physical slots on the motherboardfor memory DIMMs:

DIMM_A0 DIMM_B0
DIMM_A1 DIMM_B1

Labels for these slots are usually silk-screened on the motherboard.Slots labeledA are channel 0 in this example. Slots labeledB arechannel 1. Notice that there are two csrows possible on a physical DIMM.These csrows are allocated their csrow assignment based on the slot intowhich the memory DIMM is placed. Thus, when 1 DIMM is placed in eachChannel, the csrows cross both DIMMs.

Memory DIMMs come single or dual “ranked”. A rank is a populated csrow.In the example above 2 dual ranked DIMMs are similarly placed. Thus,both csrow0 and csrow1 are populated. On the other hand, when 2 singleranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they willhave just one csrow (csrow0) and csrow1 will be empty. The patternrepeats itself for csrow2 and csrow3. Also note that some memorycontrollers don’t have any logic to identify the memory module, seerankX directories below.

The representation of the above is reflected in the directorytree in EDAC’s sysfs interface. Starting in directory/sys/devices/system/edac/mc, each memory controller will berepresented by its ownmcX directory, whereX is theindex of the MC:

..../edac/mc/           |           |->mc0           |->mc1           |->mc2           ....

Under eachmcX directory eachcsrowX is again represented by acsrowX, whereX is the csrow index:

.../mc/mc0/        |        |->csrow0        |->csrow2        |->csrow3        ....

Notice that there is no csrow1, which indicates that csrow0 is composedof a single ranked DIMMs. This should also apply in both Channels, inorder to have dual-channel mode be operational. Since both csrow2 andcsrow3 are populated, this indicates a dual ranked set of DIMMs forchannels 0 and 1.

Within each of themcX andcsrowX directories are several EDACcontrol and attribute files.

`mcX` directories¶

InmcX directories are EDAC control and attribute files forthisX instance of the memory controllers.

For a description of the sysfs API, please see:

Documentation/ABI/testing/sysfs-devices-edac

`dimmX` or`rankX` directories¶

The recommended way to use the EDAC subsystem is to look at the informationprovided by thedimmX orrankX directories[5].

A typical EDAC system has the following structure under/sys/devices/system/edac/[6]:

/sys/devices/system/edac/├── mc│   ├── mc0│   │   ├── ce_count│   │   ├── ce_noinfo_count│   │   ├── dimm0│   │   │   ├── dimm_ce_count│   │   │   ├── dimm_dev_type│   │   │   ├── dimm_edac_mode│   │   │   ├── dimm_label│   │   │   ├── dimm_location│   │   │   ├── dimm_mem_type│   │   │   ├── dimm_ue_count│   │   │   ├── size│   │   │   └── uevent│   │   ├── max_location│   │   ├── mc_name│   │   ├── reset_counters│   │   ├── seconds_since_reset│   │   ├── size_mb│   │   ├── ue_count│   │   ├── ue_noinfo_count│   │   └── uevent│   ├── mc1│   │   ├── ce_count│   │   ├── ce_noinfo_count│   │   ├── dimm0│   │   │   ├── dimm_ce_count│   │   │   ├── dimm_dev_type│   │   │   ├── dimm_edac_mode│   │   │   ├── dimm_label│   │   │   ├── dimm_location│   │   │   ├── dimm_mem_type│   │   │   ├── dimm_ue_count│   │   │   ├── size│   │   │   └── uevent│   │   ├── max_location│   │   ├── mc_name│   │   ├── reset_counters│   │   ├── seconds_since_reset│   │   ├── size_mb│   │   ├── ue_count│   │   ├── ue_noinfo_count│   │   └── uevent│   └── uevent└── uevent

In thedimmX directories are EDAC control and attribute files forthisX memory module:

size - Total memory managed by this csrow attribute file
This attribute file displays, in count of megabytes, the memorythat this csrow contains.
dimm_ue_count - Uncorrectable Errors count attribute file
This attribute file displays the total count of uncorrectableerrors that have occurred on this DIMM. If panic_on_ue is setthis counter will not have a chance to increment, since EDACwill panic the system.
dimm_ce_count - Correctable Errors count attribute file
This attribute file displays the total count of correctableerrors that have occurred on this DIMM. This count is veryimportant to examine. CEs provide early indications that aDIMM is beginning to fail. This count field should bemonitored for non-zero values and report such informationto the system administrator.
dimm_dev_type - Device type attribute file
This attribute file will display what type of DRAM device isbeing utilized on this DIMM.Examples:
x1
x2
x4
x8
dimm_edac_mode - EDAC Mode of operation attribute file
This attribute file will display what type of Error detectionand correction is being utilized.
dimm_label - memory module label control file
This control file allows this DIMM to have a label assignedto it. With this label in the module, when errors occurthe output can provide the DIMM label in the system log.This becomes vital for panic events to isolate thecause of the UE event.
DIMM Labels must be assigned after booting, with informationthat correctly identifies the physical slot with itssilk screen label. This information is currently verymotherboard specific and determination of this informationmust occur in userland at this time.
dimm_location - location of the memory module
The location can have up to 3 levels, and describe how thememory controller identifies the location of a memory module.Depending on the type of memory and memory controller, itcan be:
csrow andchannel - used when the memory controllerdoesn’t identify a single DIMM - e. g. inrankX dir;
branch,channel,slot - typically used on FB-DIMM memorycontrollers;
channel,slot - used on Nehalem and newer Intel drivers.
dimm_mem_type - Memory Type attribute file
This attribute file will display what type of memory is currentlyon this csrow. Normally, either buffered or unbuffered memory.Examples:
Registered-DDR
Unbuffered-DDR

[5] On some systems, the memory controller doesn’t have any logicto identify the memory module. On such systems, the directory is calledrankX and works on a similar way as thecsrowX directories.On modern Intel memory controllers, the memory controller identifies thememory modules directly. On such systems, the directory is calleddimmX.

[6]	There are also some`power` directories and`subsystem`symlinks inside the sysfs mapping that are automatically created bythe sysfs subsystem. Currently, they serve no purpose.

`csrowX` directories¶

When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain thecsrowXdirectories. As this API doesn’t work properly for Rambus, FB-DIMMs andmodern Intel Memory Controllers, this is being deprecated in favor ofdimmX directories.

In thecsrowX directories are EDAC control and attribute files forthisX instance of csrow:

ue_count - Total Uncorrectable Errors count attribute file
This attribute file displays the total count of uncorrectableerrors that have occurred on this csrow. If panic_on_ue is setthis counter will not have a chance to increment, since EDACwill panic the system.
ce_count - Total Correctable Errors count attribute file
This attribute file displays the total count of correctableerrors that have occurred on this csrow. This count is veryimportant to examine. CEs provide early indications that aDIMM is beginning to fail. This count field should bemonitored for non-zero values and report such informationto the system administrator.
size_mb - Total memory managed by this csrow attribute file
This attribute file displays, in count of megabytes, the memorythat this csrow contains.
mem_type - Memory Type attribute file
This attribute file will display what type of memory is currentlyon this csrow. Normally, either buffered or unbuffered memory.Examples:
Registered-DDR
Unbuffered-DDR
edac_mode - EDAC Mode of operation attribute file
This attribute file will display what type of Error detectionand correction is being utilized.
dev_type - Device type attribute file
This attribute file will display what type of DRAM device isbeing utilized on this DIMM.Examples:
x1
x2
x4
x8
ch0_ce_count - Channel 0 CE Count attribute file
This attribute file will display the count of CEs on thisDIMM located in channel 0.
ch0_ue_count - Channel 0 UE Count attribute file
This attribute file will display the count of UEs on thisDIMM located in channel 0.
ch0_dimm_label - Channel 0 DIMM Label control file
This control file allows this DIMM to have a label assignedto it. With this label in the module, when errors occurthe output can provide the DIMM label in the system log.This becomes vital for panic events to isolate thecause of the UE event.
DIMM Labels must be assigned after booting, with informationthat correctly identifies the physical slot with itssilk screen label. This information is currently verymotherboard specific and determination of this informationmust occur in userland at this time.
ch1_ce_count - Channel 1 CE Count attribute file
This attribute file will display the count of CEs on thisDIMM located in channel 1.
ch1_ue_count - Channel 1 UE Count attribute file
This attribute file will display the count of UEs on thisDIMM located in channel 0.
ch1_dimm_label - Channel 1 DIMM Label control file
This control file allows this DIMM to have a label assignedto it. With this label in the module, when errors occurthe output can provide the DIMM label in the system log.This becomes vital for panic events to isolate thecause of the UE event.
DIMM Labels must be assigned after booting, with informationthat correctly identifies the physical slot with itssilk screen label. This information is currently verymotherboard specific and determination of this informationmust occur in userland at this time.

System Logging¶

If logging for UEs and CEs is enabled, then system logs will containinformation indicating that errors have been detected:

EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edacEDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac

The structure of the message is:

Content Example
The memory controller MC0
Error type CE
Memory page 0x283
Offset in the page 0xce0
The byte granularityor resolution of the error grain 8
The error syndrome 0xb741
Memory row row 0
Memory channel channel 1
DIMM label, if set prior DIMM B1
And then an optional, driver-specificmessage that may have additionalinformation.

Content	Example
The memory controller	MC0
Error type	CE
Memory page	0x283
Offset in the page	0xce0
The byte granularityor resolution of the error	grain 8
The error syndrome	0xb741
Memory row	row 0
Memory channel	channel 1
DIMM label, if set prior	DIMM B1
And then an optional, driver-specificmessage that may have additionalinformation.

Both UEs and CEs with no info will lack all but memory controller, errortype, a notice of “no info” and then an optional, driver-specific errormessage.

PCI Bus Parity Detection¶

On Header Type 00 devices, the primary status is looked at for anyparity error regardless of whether parity is enabled on the device ornot. (The spec indicates parity is generated in some cases). On HeaderType 01 bridges, the secondary status register is also looked at to seeif parity occurred on the bus on the other side of the bridge.

Sysfs configuration¶

Under/sys/devices/system/edac/pci are control and attribute files asfollows:

check_pci_parity - Enable/Disable PCI Parity checking control file
This control file enables or disables the PCI Bus Parity scanningoperation. Writing a 1 to this file enables the scanning. Writinga 0 to this file disables the scanning.
Enable:
echo "1" >/sys/devices/system/edac/pci/check_pci_parity
Disable:
echo "0" >/sys/devices/system/edac/pci/check_pci_parity
pci_parity_count - Parity Count
This attribute file will display the number of parity errors thathave been detected.

Module parameters¶

edac_mc_panic_on_ue - Panic on UE control file
An uncorrectable error will cause a machine panic. This is usuallydesirable. It is a bad idea to continue when an uncorrectable erroroccurs - it is indeterminate what was uncorrected and the operatingsystem context might be so mangled that continuing will lead to furthercorruption. If the kernel has MCE configured, then EDAC will nevernotice the UE.
LOAD TIME:
module/kernel parameter: edac_mc_panic_on_ue=[0|1]
RUN TIME:
echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
edac_mc_log_ue - Log UE control file
Generate kernel messages describing uncorrectable errors. These errorsare reported through the system message log system. UE statisticswill be accumulated even when UE logging is disabled.
LOAD TIME:
module/kernel parameter: edac_mc_log_ue=[0|1]
RUN TIME:
echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
edac_mc_log_ce - Log CE control file
Generate kernel messages describing correctable errors. Theseerrors are reported through the system message log system.CE statistics will be accumulated even when CE logging is disabled.
LOAD TIME:
module/kernel parameter: edac_mc_log_ce=[0|1]
RUN TIME:
echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
edac_mc_poll_msec - Polling period control file
The time period, in milliseconds, for polling for error information.Too small a value wastes resources. Too large a value might delaynecessary handling of errors and might loose valuable information forlocating the error. 1000 milliseconds (once each second) is the currentdefault. Systems which require all the bandwidth they can get, mayincrease this.
LOAD TIME:
module/kernel parameter: edac_mc_poll_msec=[0|1]
RUN TIME:
echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
panic_on_pci_parity - Panic on PCI PARITY Error
This control file enables or disables panicking when a parityerror has been detected.
module/kernel parameter:
edac_panic_on_pci_pe=[0|1]
Enable:
echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
Disable:
echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe

EDAC device type¶

In the header file, edac_pci.h, there is a series of edac_device structuresand APIs for the EDAC_DEVICE.

User space access to an edac_device is through the sysfs interface.

At the location/sys/devices/system/edac (sysfs) new edac_device deviceswill appear.

There is a three level tree beneath the aboveedac directory. For example,thetest_device_edac device (found at thehttp://bluesmoke.sourceforget.netwebsite) installs itself as:

/sys/devices/system/edac/test-instance

in this directory are various controls, a symlink and one or moreinstancedirectories.

The standard default controls are:

log_ce boolean to log CE events
log_ue boolean to log UE events
panic_on_ue boolean topanic the system if an UE is encountered(default off, can be set true via startup script)
poll_msec time period between POLL cycles for events

The test_device_edac device adds at least one of its own custom control:

test_bits which in the current test driver does nothing butshow how it is installed. A ported driver canadd one or more such controls and/or attributesfor specific uses.One out-of-tree driver uses controls here to allowfor ERROR INJECTION operations to hardwareinjection registers

The symlink points to the ‘struct dev’ that is registered for this edac_device.

Instances¶

One or more instance directories are present. For thetest_device_edaccase:

test-instance0

In this directory there are two default counter attributes, which are totals ofcounter in deeper subdirectories.

ce_count total of CE events of subdirectories
ue_count total of UE events of subdirectories

Blocks¶

At the lowest directory level is theblock directory. There can be 0, 1or more blocks specified in each instance:

test-block0

In this directory the default attributes are:

ce_count which is counter of CE events for thisblockof hardware being monitored
ue_count which is counter of UE events for thisblockof hardware being monitored

Thetest_device_edac device adds 4 attributes and 1 control:

test-block-bits-0 for every POLL cycle this counteris incremented
test-block-bits-1 every 10 cycles, this counter is bumped once,and test-block-bits-0 is set to 0
test-block-bits-2 every 100 cycles, this counter is bumped once,and test-block-bits-1 is set to 0
test-block-bits-3 every 1000 cycles, this counter is bumped once,and test-block-bits-2 is set to 0
reset-counters writing ANY thing to this control willreset all the above counters.

Use of thetest_device_edac driver should enable any others to create their ownunique drivers for their hardware systems.

Thetest_device_edac sample driver is located at thehttp://bluesmoke.sourceforge.net project site for EDAC.

Usage of EDAC APIs on Nehalem and newer Intel CPUs¶

On older Intel architectures, the memory controller was part of the NorthBridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake andnewer Intel architectures integrated an enhanced version of the memorycontroller (MC) inside the CPUs.

This chapter will cover the differences of the enhanced memory controllersfound on newer Intel CPUs, such asi7core_edac,sb_edac andsbx_edac drivers.