Quartus® Prime Design Software

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A powerful, integrated design environment built to scale with your FPGA designs. From design entry and synthesis to optimization, verification, and simulation, Quartus Prime supports every step of development—enabling advanced performance on devices with millions of logic elements.

WHAT'S NEW

What's New in Version 25.3

Power & Thermal Analyzer

Next generation tool with Graphical reports, sortable columns, hierarchy first display, resource view, recalculation button, partial import/export, and standalone installer.
Automation Support for whatif scenarios: With TCL scripting, explore alternate package/OPN combinations to optimize power.
Enhanced validation and debug usability with locatable validation errors and editable rows
Advanced thermal workflow calculation modes now accounts for % heat through heat sinks.
Heatsink design guidance: model dissipation paths and evaluate cooling strategies.

Visual Designer Studio (Beta)

Public Beta launch with no-cost license.
New Block Diagram canvas.
AXI4Lite support across interconnect and verification.
Address map viewer enhancements
Language templates, SystemVerilog wrapper generation, hierarchy support, and conduit/connect infrastructure.
Nios V example designs and system designs delivery via GitHub.

New Device & Model Support

Final and preliminary device, timing, and power support across multiple Agilex 3, Agilex 5, and Agilex 7
Runtime and memory optimizations in device models for faster compile times and smaller footprint.

Compiler, QoR & Safety

Safety Separation Flow: support in Assembler with basic I/O preservation and related clock-preservation enablement.
Revision/version-control methodology updates for Archiver.

System-Level Debug & System Console

Streaming-capable System Console with memory-map commands
Remote debug over streaming enhancements.
HPS SEU monitoring support for Agilex 7
System ID enhancements with HAL driver support.

Quartus GUI & Usability

Chip Planner: total resources shown for drawn LogicLock regions.
Unified GUI elements for DR/DS tools; simplified clocking for Dynamic Reconfig.
Licensing data in IP Catalog for faster discovery.
Streamlined Signing & Encryption tool UI.

Installation, Packaging & Infrastructure / Cloud

AI Suite is selectable as an addon or standalone tool.
Unified installation experience with dynamic component selection and persona/workload profiles.
Containers: Ubuntu 22 build container; Docker for Quartus Embedded Edition.
New “Embedded-Centric” Edition of Quartus.

DSP Builder

Multi-Layer Perceptron block added to DSP Builder – helps integrate DSP Builder with MATLAB’s Machine Learning Toolboxes to deploy AI on FPGAs.
New blocks added functionalities: can import trained networks from MATLAB Deep Learning Toolbox, and activation functions, full parallel layers, and time-shared blocks enable computing control and tuning of neural network.
ML & Neural network example designs added for image classification, to apply digital predistortion in a power amplifier, and channel estimation for 5G OFDM system.

Nios V & Embedded Software

FreeRTOS enablement: TCP/IP stack; drivers for TSE, mSGDMA, QSPI, JTAG UART, LW UART, System ID, Parallel I/O, Interval Timer
System ID support in FreeRTOS
Nios V/m SW based ECC full support
System ID- auto hash generation
SignalTap plugin for Nios V
Full GHRD across dev kits with migration of designs to GitHub
Linux UX improvements, Yocto/Roll-your-own
Windriver VxWorks BSP support for Agilex 5

Features and Improvements

Agilex 3 Production support, also including hostless JTAG design Agilex™ 5 C-Series dev kit.
One stop install: available as option in Quartus installer.
Windows support

AI Models and Example Designs

FPGA AI Suite example designs are available in Visual Designer Studio (Beta)
DDR free mode enables instantaneous model switching, lower power, higher FPS
- Example: 27% increase in FPS for RESNET-50 on Agilex 7

Ethernet / Networking IP

F-Tile MR Ethernet: new DR group covering 400/200/100/50/25/10GE.
TSN MAC system examples (multi-port static data rates) and IEEE 1588 PTP 10G rev-A validation.
TSE soft IP + hard MAC/PHY dynamic reconfiguration (with & without PTP/SyncE); DR toolkit enablement.
SM_ETH HVIO PLL coverage expansions (TSE, MRIP variants, PTP modes, LL10G/MGEPHY).

PCI Express

Agilex 7 F-Tile: AVMM Root Port x4 support added.
Agilex 7 F-Tile: Added DWORD-aligned to endpoint memory addressing for AVST PCIe BFM.
Agilex 7 R-Tile: 2 x8 design example including support for pkt / traffic generation, and DMA, BAM mode support for AXI user interface.
SR-IOV design examples added for Agilex 5 and Agilex 3 devices.
Agilex 5: additional design example supporting AXI-MM for DMA mode.
Agilex 5: added flexibility to AXI-ST MCDMA design example to allow data widths selection to extend support for multiple lane widths for PCIe 3.0 / 4.0.
Agilex 3: AXI Stream PCI Express IP achieves hardware validation.

CXL 2.0

Agilex 7 I-Series: added 4-slice Type 3 design example (4 EMIFs) - SCT.
GUI parameter for CXL 2.0 compliance – 2.0 features capability shown through DVSEC registers.
Agilex 7 I/M-Series: Hooks for enabling customer to implement Multi-Logic Device (MLD) feature (included in BASEHIP design RTL and BASEHIP design example) - SCT.

JESD / CPRI / Serial Lite / PHY

JESD204C increased the number of converters per device (M > 32) support for Agilex 5
CPRI intra-protocol DR example designs (all 12 variants); additional HVIO PLL enablement across CPRI/JESD/SL4.
Serial Lite: toolkit-friendly reset CSRs (per DPHY spec).

Video & Display Connectivity

AXIS-VVP full interface added for HDMI 2.0 and SDI Audio with support up to 12G now available on Agilex 5.
Diagnostic Toolkit (DPTK) with GUI for DisplayPort.
MIPI CSI-2/DSI-2 enablement on Agilex 3 devices; SDI Audio on Agilex 3; SoC video output path validation.

Memory & EMIF

PHYLite IO delay @ 3.2 Gbps for IO96B (FP8).
EMIF toolkit enablement for Agilex 5 HPS EMIF IP.
Agilex 3 development kit example designs for LPDDR4 and MIPI / DisplayPort.
DDR5-5600 LP5 5500 max speeds supported for Agilex 5D.

Soft IP & Misc

Soft I3C controller; System ID timestamp/HASH features; ALT_ECC and FIFO IP updates targeting FuSa needs.
Safety certification packaging (FSDP) for QPDS.
Methodology: revision/version control improvements for Archiver.

Downloads

Quartus Prime

Pro Edition

Advanced design flow, block-based design, interface planner, partial reconfiguration, and high-speed transceiver support

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Quartus Prime

Standard Edition

Broad legacy support, platform designer, partial reconfiguration, and core timing/power tools

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Quartus Prime

Lite Edition

Free access, essential design tools, basic compile flow, Signal Tap, and starter simulation

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Features

Platform Designer

Platform Designer is a system integration tool in the Quartus® Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process.

Documentation Video Details

Block-Based Design

Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device.

Documentation Video Details

Partial Reconfiguration

Reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

Documentation Video

Design Partition Planner

A design partition is a logical, named, hierarchical boundary that you can assign to an instance in your design. Defining a design partition allows you to optimize and lock down the compilation results for individual blocks.

Documentation

Chip Planner

Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter.

Documentation

Interface Planner

The Interface Planner explores a device’s peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legality checks in real-time.

Documentation

Logic Lock Regions

A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region.

Documentation

Multiprocessor Support (Faster Compile Time)

Using multi-processors for compilation can result in faster compile times depending on the number of cores used.

Documentation

IP Base Suite

Altera provides full production licenses for some of its popular IP cores in the Altera FPGA IP Base Suite, which is free with the Quartus Prime Software and Quartus Prime Pro Edition Software.

Documentation

Fitter (Place and Route)

The Compiler's Fitter performs design placement and routing. During place and route, the Fitter determines the best placement and routing of logic in the target FPGA device.

Documentation

Register Retiming

Register Retiming can balance register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric.

Documentation

Timing Analyzer

The Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology.

Documentation

Design Space Explorer II

The Design Space Explorer II tool allows you to find optimal project settings for resource, performance, or power optimization goals.

Documentation

Power Analysis

Power analysis features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that give you the ability to estimate power consumption.

Documentation

Signal Tap Logic Analyzer

The Signal Tap logic analyzer captures and displays the real-time signal behavior in an FPGA design allowing you to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.

Transceiver Toolkit

Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time.

Documentation Details

Questa*-FPGA Edition Software

Questa*-FPGA software editions are a version of the Siemens EDA Questa* Core software targeted for Altera® FPGAs devices.

Documentation Download