wishbone
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A small, light weight, RISC CPU soft core
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Feb 6, 2025 - Verilog
Bus bridges and other odds and ends
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Feb 5, 2025 - Verilog
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
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Jan 4, 2025 - Verilog
A utility for Composing FPGA designs from Peripherals
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Dec 23, 2024 - C++
Simple UART controller for FPGA written in VHDL
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Aug 7, 2021 - VHDL
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
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Dec 3, 2024 - Assembly
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
A wishbone controlled FM transmitter hack
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Jan 16, 2024 - Verilog
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
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Jun 3, 2023 - Verilog
VexRiscV system with GDB-Server in Hardware
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Jul 5, 2023 - VHDL
A caravan equipped with API for creating bus protocols in Chisel with ease.
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Nov 20, 2024 - Scala
RISC-V Ibex core with Wishbone B4 interface
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Dec 24, 2019 - HTML
HDL components to build a customized Wishbone crossbar switch
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May 30, 2019 - SystemVerilog
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