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#

wishbone

Here are 54 public repositories matching this topic...

A small, light weight, RISC CPU soft core

  • UpdatedFeb 6, 2025
  • Verilog

Bus bridges and other odds and ends

  • UpdatedFeb 5, 2025
  • Verilog

A simple, basic, formally verified UART controller

  • UpdatedJan 29, 2024
  • Verilog

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

  • UpdatedJan 4, 2025
  • Verilog

A utility for Composing FPGA designs from Peripherals

  • UpdatedDec 23, 2024
  • C++

An Open Source configuration of the Arty platform

  • UpdatedJan 17, 2024
  • Verilog

Simple UART controller for FPGA written in VHDL

  • UpdatedAug 7, 2021
  • VHDL

A wishbone controlled scope for FPGA's

  • UpdatedJan 12, 2024
  • Verilog
lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

  • UpdatedDec 3, 2024
  • Assembly

A collection of debugging busses developed and presented at zipcpu.com

  • UpdatedJan 18, 2024
  • Verilog

CMod-S6 SoC

  • UpdatedJan 6, 2018
  • Verilog

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

  • UpdatedNov 29, 2021
  • VHDL

A wishbone controlled FM transmitter hack

  • UpdatedJan 16, 2024
  • Verilog

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

  • UpdatedJun 3, 2023
  • Verilog

VexRiscV system with GDB-Server in Hardware

  • UpdatedJul 5, 2023
  • VHDL

A caravan equipped with API for creating bus protocols in Chisel with ease.

  • UpdatedNov 20, 2024
  • Scala

RISC-V Ibex core with Wishbone B4 interface

  • UpdatedDec 24, 2019
  • HTML
WbXbc

HDL components to build a customized Wishbone crossbar switch

  • UpdatedMay 30, 2019
  • SystemVerilog
MPSoC-DMA

Direct Access Memory for MPSoC

  • UpdatedMar 16, 2025
  • SystemVerilog
fpga-3-softcores

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

  • UpdatedAug 24, 2020
  • Verilog

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