vexriscv

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efabless /caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

UpdatedFeb 26, 2025
Verilog

chipsalliance /f4pga-examples

Star272

Example designs showing different ways to use F4PGA toolchains.

fpga verilog litex conda-packages fpga-designs vexriscv symbiflow-toolchains f4pga

UpdatedMar 27, 2024
Verilog

BLangOS /VexRiscV_with_HW-GDB_Server

Star20

VexRiscV system with GDB-Server in Hardware

microcontroller vhdl fpga-soc risc-v c-language wishbone rsp gdbserver vexriscv

UpdatedJul 5, 2023
VHDL

xThaid /fpga-lb

Star18

A toy L4 load balancer running on FPGA

networking fpga ocaml load-balancer riscv freertos dataflow verilator quartus vexriscv hardcaml

UpdatedFeb 28, 2022
C

jmio /ECP5_Brieysoc

Star8

Briey SoC on ECP5 (ICESugar Pro)

risc-v ecp5 vexriscv icesugar icesugar-pro

UpdatedMar 26, 2022
Verilog

jmio /testvex

Star7

Briey SoC on Sipeed Tang Primer

risc-v vexriscv sipeed-tang-primer

UpdatedMar 26, 2022
Verilog

mcejp /Poly94

Star3

Yet another faux-retro game system

fpga yosys cocotb prjtrellis ulx3s vexriscv

UpdatedMar 3, 2024
Verilog

lnis-uofu /OpenFPGA-Softcores

Star2

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

picorv32 openfpga ibex vexriscv

UpdatedJul 3, 2022
Python

neunzehnhundert97 /VexRiscv-Instruction-Framework

Star2

A small framework to simplify the creation of custom instruction for the VexRiscv.

risc-v vexriscv

UpdatedJan 6, 2022
Scala

supleed2 /EIE4-FYP

Sponsor

Star0

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

embedded-systems systemverilog can-bus audio-synthesis risc-v cordic litex ecp5 waveform-generator vexriscv orangecrab stacksynth

UpdatedJan 19, 2024
Python

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