A High-performance Timing Analysis Tool for VLSI Systems

• UpdatedMay 26, 2023
• Verilog

The next generation of OpenLane, rewritten from scratch with a modular architecture

• UpdatedFeb 26, 2025
• Python

ESP32 好玩、有趣、实用的项目

• UpdatedMay 23, 2017
• C

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

• UpdatedMay 28, 2024
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A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

• UpdatedAug 7, 2022
• C++

Linux generic dhcp snooping daemon using nflog and ebtables or nftables

• UpdatedNov 16, 2022
• C

Static Timing Analysis Full Course

• UpdatedJan 14, 2023

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

• UpdatedJul 21, 2020
• Coq

Free and extensible software that helps you keep track of you coding statistics

• UpdatedApr 17, 2020
• Python

EHR DREAM Challenge

• UpdatedMar 27, 2020

SensorThings work at DataCove

• UpdatedMar 30, 2019

Ceates a bidirectional link between UDP sockets and Serial port via ESP8266

• UpdatedNov 1, 2020
• C++

⚙️ A Sensor Things API parser

• UpdatedJul 11, 2023
• Python

Parse tokens from an string into an array

• UpdatedSep 2, 2018
• Python

State Tag Application in Vue.js

• UpdatedDec 12, 2024
• JavaScript

This repository encompasses all aspects of Hardware ASIC design, From RTL to GDS II, including Verilog, Synth, PD and Signoff (STA, PDN, etc.)

• UpdatedJan 29, 2025
• Ruby

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

• UpdatedNov 25, 2024
• Verilog

毕业设计代码【规范版本】

• UpdatedMay 19, 2022
• C

Silicon Highway Technologies Free STA, ASTA Timing Engine

• UpdatedFeb 26, 2025

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

• UpdatedJul 13, 2024
• Tcl