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google /skywater-pdk

Star3.1k

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

UpdatedOct 28, 2024
Python

The-OpenROAD-Project /OpenLane

Star1.4k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

UpdatedFeb 26, 2025
Python

SparcLab /OpenSERDES

Star150

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

serdes skywater digitalarchitecture openlane openpdk

UpdatedMar 26, 2022
Verilog

google /sky90fd-pdk

Star109

magic asic eda spice ic klayout silicon integrated-circuits ngspice xyce skywater xschem sky90fd fdsoi

UpdatedMay 11, 2023

google /open-source-pdks

Star92

Index of the fully open source process design kits (PDKs) maintained by Google.

asic eda silicon pdk openroad skywater 130nm sky130 180nm globalfoundries gf180mcu

UpdatedSep 4, 2022

google /skywater-pdk-libs-sky130_fd_pr_reram

Star37

SKY130 ReRAM and examples (SkyWater Provided)

asic eda silicon ngspice xyce pdk openroad reram skywater 130nm

UpdatedApr 20, 2022

w32agobot /SKY130_SAR-ADC

Star32

Fully-differential asynchronous non-binary 12-bit SAR-ADC

master-thesis adc skywater sky130

UpdatedJun 13, 2023
Verilog

sgherbst /sky130-hello-world

Star23

Minimal SKY130 example with self-checking LVS, DRC, and PEX

magic eda spice netgen inverter pdk skywater

UpdatedJan 20, 2021
Shell

stineje /sky130_cds

Star21

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

eda verilog vlsi cadence skywater

UpdatedJul 25, 2023
Tcl

google /skywater-pdk-actions

Star12

GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @https://github.com/google/skywater-pdk

asic digital ci actions cicd logic-gates pdk github-actions skywater

UpdatedJun 3, 2021
Python

kbeckmann /caravel-pll-calculator

Sponsor

Star10

PLL configuration generator for the Caravel management core

caravel skywater openlane

UpdatedMay 7, 2021
Python

VardhanSuroshi /VLSI-ASIC-Design-Flow

Star10

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

opensource rtl vlsi risc-v vlsi-physical-design vlsi-design asic-design skywater openlane