【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

• UpdatedJul 12, 2020
• Coq

SDRAM controller with AXI4 interface

• UpdatedAug 8, 2019
• C++

SDRAM controller optimized to a memory bandwidth of 316MB/s

• UpdatedAug 16, 2021
• Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

• UpdatedJun 19, 2024
• Verilog

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

• UpdatedJul 8, 2021
• Verilog

Simple SDRAM Controller for DE10-Lite.

• UpdatedJan 20, 2019
• Verilog

SDRAM Tester implemented in FPGA

• UpdatedMay 1, 2021
• VHDL

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

• UpdatedJul 1, 2022
• HTML

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

• UpdatedOct 30, 2017
• Verilog

A HDL SDRAM controller designed for retro hardware and FPGAs

• UpdatedJun 25, 2023
• SystemVerilog

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

• UpdatedOct 15, 2023
• Verilog

SDRAM controller

• UpdatedAug 15, 2024
• Verilog

SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]

• UpdatedApr 11, 2022
• Verilog

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

• UpdatedOct 21, 2024
• Verilog

High-Speed SystemVerilog SDRAM Controller

• UpdatedJan 27, 2024
• SystemVerilog

🛠 A SDRAM controller in Verilog HDL

• UpdatedMar 21, 2022
• Verilog

Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required

• UpdatedOct 10, 2020