Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

• UpdatedSep 17, 2022

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

• UpdatedFeb 22, 2022

In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

• UpdatedAug 19, 2024

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

• UpdatedJul 19, 2022
• Verilog

The SAP-1 in Verilog, and now as an ASIC!

• UpdatedNov 5, 2022
• Verilog

This is part of EC383 - Mini Project in VLSI Design.

• UpdatedMay 8, 2022
• Verilog

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

• UpdatedFeb 25, 2021

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

• UpdatedApr 17, 2024

This is my openlane repository in which we perform synthesis of our design/module.

• UpdatedMar 17, 2024
• Tcl

VSDMemSOC Implementation flow:: RTL2GDSII

• UpdatedMar 1, 2024
• Verilog

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

• UpdatedMar 8, 2024
• Verilog

Adding a Customized Standard Cell into the OpenLane Flow

• UpdatedMar 5, 2024

TinyTapeout GDS blackbox macro testing

• UpdatedSep 9, 2024
• Python

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

• UpdatedMar 5, 2025
• Verilog

Complete RTL to GDSII flow of a picorv32a core

• UpdatedSep 18, 2024