#
ml-for-chip-design
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This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
reinforcement-learningdeep-learningmctslogic-synthesiselectronic-design-automationboolean-optimizationelectronic-designmcts-agentsiclr2024abc-rlretrieval-guided-rlboolean-circuit-minimizationml-for-logic-synthesisml-for-chip-design
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May 10, 2024 - Verilog
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