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chipyard

Here are 10 public repositories matching this topic...

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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  • UpdatedMar 19, 2025
  • Scala

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

  • UpdatedDec 5, 2024
  • Python

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

  • UpdatedDec 1, 2022
  • C

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

  • UpdatedFeb 7, 2022
  • Verilog

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

  • UpdatedJun 19, 2020
  • Verilog

An online viewer for Chipyard output files

  • UpdatedOct 21, 2021
  • TypeScript

This Github repository serves as a User Guide (UG) for new Chipyard users.

  • UpdatedJun 14, 2024
  • Python
  • UpdatedAug 1, 2021
  • Scala

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