branch-prediction
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32-bit Superscalar RISC-V CPU
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Sep 18, 2021 - Verilog
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
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Jun 11, 2022 - C++
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
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Jul 2, 2020 - C++
Advanced Architecture Labs with CVA6
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Jan 16, 2024 - SystemVerilog
Super scalar Processor design
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Sep 7, 2014 - Verilog
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
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Apr 10, 2021 - C++
Kite: Architecture Simulator for RISC-V Instruction Set
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Jan 2, 2025 - C++
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
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Jul 4, 2024 - Jupyter Notebook
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
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Apr 26, 2018 - C++
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
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May 19, 2020 - C++
Computer architecture related projects
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Nov 17, 2017 - C++
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
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Dec 26, 2020 - SystemVerilog
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
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Oct 27, 2021 - Python
VHDL code of three branch predictors
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Jul 15, 2019 - VHDL
System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.
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Sep 11, 2018 - Java
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
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Apr 20, 2017 - VHDL
2 bit saturated branch predictor with BHR (Branch History Register)
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Dec 20, 2019 - C++
Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.
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Jun 4, 2020 - C#
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