Repository files navigation

This depository consists of a series of debugging bus interfaces.

Each interface connects an external debug port, whether UART, SPI, JTAG, orRPI Parallel port, to the master port of a wishbonebus. Hence, the debug interface allows you access to any device located onthe wishbone bus--both to read from and write to that bus.

It is my intention to use the various components of each of the busses asteaching tools on theZipCPU blog. Indeed, if youlook at thetopics page of the blog, you'llsee that the series is now complete.

All of the files in this repository are licensed by either GPLv3 or the LGPL.For example, the simpleHEXBUS interface is licensed under the LGPL, whereasthe other interfaces are (or will be) licensed under GPL.Should the license provided be insufficient for your needs, please feel freeto contact me for the terms necessary for a more appropriate license.