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An impplementation of 20-bit ISA.

The single-cycle implementation follows the below data path:

opcode in all R-type instruction is "0000".

instructions include: add, sub, mul, div, and, or

instructions include: bnq, lw, sw, andi, ori

HDL: ISE(Language: Verilog)

Design: Logisim

Assembler: Python

Run the following command in assembler.

ori 1 1 10ori 2 2 4add 3 1 2sub 4 1 2mul 5 1 2and 7 1 2or 8 1 2sw 1 0 0lw 9 0 0bnq 3 3 20bnq 3 4 30

Run HDL using machine code in binary and Logisim in hex.

• Sheida Abedpour
• Matin Azami
• Asal Khaef