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1. VSDMemSOCVSDMemSOCPublic

   VSDMemSOC Implementation flow:: RTL2GDSII

   Verilog 1

2. tt07_cdc_fifott07_cdc_fifoPublic

   Tapeout of "Clock Domain Crossing FIFO" module using Tinytapeout(tt07) shuttle

   SystemVerilog 2

3. TCL_ScriptingTCL_ScriptingPublic

   TCL Script to automate the generation of Pre-layout QoR results

   Verilog

4. RISC-V_HDPRISC-V_HDPPublic

   Design of a Customizable RISC-V SoC for Clapswitch Application

   Verilog 1