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1. ip_amba_ahb_ms_rtl_vip_amba_ahb_ms_rtl_vPublic

   RTL design for the AMBA AHB protocol.

   SystemVerilog 8 3

2. ip_amba_apb_ms_rtl_vip_amba_apb_ms_rtl_vPublic

   The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )

   Verilog 14 5

3. ip_generic_custom_lfsr_generator_verilogip_generic_custom_lfsr_generator_verilogPublic

   Custom polynomial ( variable width ) LFSR ( Galios/Fib ) generator

   Shell 1 1

4. ip_parallel_custom_crc_gerator_verilogip_parallel_custom_crc_gerator_verilogPublic

   Verilog parallel CRC generation module with custom polynomial and variable width

   Perl 5 2

5. rtl_template_genrtl_template_genPublic

   Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )

   Shell 3

6. rv_namecrv_namecPublic

   RISC-V ( 32b / Single Cycle ) - "RV32I"

   Shell 2