Hi all.I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have aQuartus II. How I can use this model in this software? I have...
Hi all.I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have aQuartus II. How I can use this model in this software? I have read inmanual that verilog simulation is not supported by quartus.
I have a system that includes both C (for a microprocessor) and Verilogcode. Where these components interact, I would like to have a...
I have a system that includes both C (for a microprocessor) and Verilogcode. Where these components interact, I would like to have a singlesource file from which certain relevant constants are derived. Initially,at least, I'm looking for a way to simply generate a Verilog file from a 'C' include file. This would be pretty straightforward except forthe macros in C. (I wrote one but it...
What would be the best starter book for learning both VHDL and Verilog?As well, the book should talk about design techniques of CPLD's and...
What would be the best starter book for learning both VHDL and Verilog?As well, the book should talk about design techniques of CPLD's and FPGA's.
Hello people. I will be maintaining recent snapshots of the Icarus Verilog compilerfor the Windows platform in easy to use installers...
Hello people. I will be maintaining recent snapshots of the Icarus Verilog compilerfor the Windows platform in easy to use installers athttp://armoid.com/icarus/. I have been doing this for more than a yearnow for the people in my company so I thought, what the heck, for thesame effort I can benefit other users out there. If you have other free related goodies that can be posted th...
My client is an award winning leader in their global field, andlooking to expand their broadcast engineering team. If you are anengineer with...
My client is an award winning leader in their global field, andlooking to expand their broadcast engineering team. If you are anengineer with strong Verilog VHDL experience then we would like tohear from you. C++ and FPGA experience would be a nice to have. If youwant to be part of an unrivalled technical broadcast engineering teamthen please call us. We have 15 Long Term Contract roles ...
Hey guys, does anyone know where I can get VHDL/Verilog source for theZ8001/Z8002 processor?Thanks for any info!-Adamajcrm125@gmail.com
Hey guys, does anyone know where I can get VHDL/Verilog source for theZ8001/Z8002 processor?Thanks for any info!-Adamajcrm125@gmail.com
Hi,We currently do most (all) our embedeed FW testing on either real HW (if available), using FPGA,or using HW simulator and Verilog...
Hi,We currently do most (all) our embedeed FW testing on either real HW (if available), using FPGA,or using HW simulator and Verilog models.We are looking at performing more testing on the "Host" rather than the target, and since thisis new to our group, I am looking for suggestions and comments.BTW, we use C, currently we don't use an RTOS, but going forward, this is something that we wil...
Hi,I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the...
Hi,I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy.Is there anything out there that will allow me to represent my design in some sort of hierarchical functional blocks to us...
Hi, I need to stream audio data and control info I2C out of my PC intosome external hardware and was thinking of using a FIFO to deal withthe...
Hi, I need to stream audio data and control info I2C out of my PC intosome external hardware and was thinking of using a FIFO to deal withthe different clock boundaries.I was wondering if anyone had some startup verilog code on FIFOs, I amusing a Xilinx FPGAThanksRyan(ryan.pinto79@gmail.com)
Hi all. I have just purchased the omnivision 9650 cmos camera for myproject of image processing and i wish to interface the camera with...
Hi all. I have just purchased the omnivision 9650 cmos camera for myproject of image processing and i wish to interface the camera with theAltera DE2 FPGA board. For this I need to write the configuration inverilog code program but I do not have a clue about how to write it. Cananyone here provide any guidance? Thanks a lot. ---------------------------------------This messa...
Hi guys, Please give me some suggestions !1. I need to make a cycle accurate simulator for a dual core cpu. How do I pass external events...
Hi guys, Please give me some suggestions !1. I need to make a cycle accurate simulator for a dual core cpu. How do I pass external events like interrupts from one core to another during the simulation ?2. How does one make a "C" reference model talk to a verilog model during a simulation ? is "PLI" the only way ?Thanksthewhizkid
Hello,am New to PCB board design cycle. Working on circuit having powerPCinterfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do...
Hello,am New to PCB board design cycle. Working on circuit having powerPCinterfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do thecycle accurate Functional simulation of the above circuit.How should i go for it?Queries:1. Which tool i should use.2. Do i need to convert schematics into verilog?3. Do i need Models for all the components in the circuit. What is the p...
Hi,I need to program a couple of old small assorted brand PAL (includingGAL) chips. Is there any free software tool that can generate...
Hi,I need to program a couple of old small assorted brand PAL (includingGAL) chips. Is there any free software tool that can generate jedfiles from Verilog (or ABEL and schematic) entry so that I can exportto a universal programmer for downloading purpose? Thanks for anyhelp.CFF
Hi,I am looking at selecting a processor for our SoC platform. Currentlywe use an embedded 8051 core (small, low power, low...
Hi,I am looking at selecting a processor for our SoC platform. Currentlywe use an embedded 8051 core (small, low power, low performance,cheap).For our next project, we need more performance, and we are also tryingto create a platform suitable for all future projects.The CPU must be available as RTL (VHDL or Verilog) source.Obviously, there are lots of options- Faster 8051...
Is there UART in FPGA or whether UART has to be connnect externally..andhow can we send information from FPGA through UART to...
Is there UART in FPGA or whether UART has to be connnect externally..andhow can we send information from FPGA through UART to Ethernet........cananyone give guidence for writing coding either in VHDL or in Verilog forsending information from FPGA to Ethernet through UART
Hi,I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDLinterface with an external COLDFIRE processor. Due to...
Hi,I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDLinterface with an external COLDFIRE processor. Due to hardwareconsiderations (not mine) I need to use 9 bits of address and 16 bits ofdatas,The following signals are available on my incoming pinout : TA, TEA, CS1,IRQ1 and R/W.Has anybody a clue where I can get some VHDL/Verilog code to help me?Thanks in adv...
http://bknpk.no-ip.biz/cpu_8051_ver/top.html#Stable Design: The design is translated from a VHDL dalton...
http://bknpk.no-ip.biz/cpu_8051_ver/top.html#Stable Design: The design is translated from a VHDL dalton projecthttp://www.cs.ucr.edu/~dalton/i8051/i8051syn.#Small Design: Consumes only 324 Flip-Flops: map report#Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
Hello: I want to know about hot fields of working in FPGA.I am doingcomputer engineering and want to do FPGA related project.I also...
Hello: I want to know about hot fields of working in FPGA.I am doingcomputer engineering and want to do FPGA related project.I also want tolearn about the sub fields in FPGA.I have a good command in verilog butnearly zero knowledge about FPGA's.Please give me data related withFPGA project selection and FPGA related projects.Any comments oranswers are highly encouraged and apprec...
Hello,Let me right again in this forum on the same topic. But know inEnglish. Whatever my English is very poor.I am working for about 4...
Hello,Let me right again in this forum on the same topic. But know inEnglish. Whatever my English is very poor.I am working for about 4 month's ego with an ML405 Xilinx Virtex 4board and I wanted now to implement a Software Defined Radio (SDR).I understand everything that relates to SDR (theory, operation,Etc..) Very good. Likewise, I also understand VHDL and VERILOG.Now I would li...
Hello,I have put up an article on our web site that describes a RISC CPU IP Corethat was created for one of our...
Hello,I have put up an article on our web site that describes a RISC CPU IP Corethat was created for one of our clients:http://www.summitsoftconsulting.com/Pic10IpCore.htmThe RISC IP Core is instruction-compatible with the MicrochipPIC10F200-series of microcontrollers. Full design documentation is availableas well as full Verilog source code (including a full set of test benches)....
