Hi,I debated putting this announcement here, however, if you are doingASIC, or FPGA embedded design, this might be of help.I recently...
Hi,I debated putting this announcement here, however, if you are doingASIC, or FPGA embedded design, this might be of help.I recently created a Google custom search engine called ChipHit athttp://www.chiphit.com. Please take a look and provide suggestions.I spend many hours a day searching the internet for ASIC, FPGA, andEDA tool topics as I am ASIC/FPGA applications engineer. F...
My problem is to test my driver software ,but the asic chip is notready yet.I can simulate the registers of the asic easyly,but theHW...
My problem is to test my driver software ,but the asic chip is notready yet.I can simulate the registers of the asic easyly,but theHW interrupts which will be generated by asic chip is necessary totest my interrupt handler and interrupt driven SW.For X86 processor I know that also SW interrupt generation is possiblebut how?How should I write interrupt handler for a SW interrupt?Does...
Dear All,I have plans to work on ASIC based on ARM926EJ-S core. I am planning toport the Nucleus RTOS to the ASIC.I find the ARM core is...
Dear All,I have plans to work on ASIC based on ARM926EJ-S core. I am planning toport the Nucleus RTOS to the ASIC.I find the ARM core is well supported in the Nucleus RTOS.How to analyze the porting requirements to a supported processor butfor different set of peripherals?I have downloaded the NucleusSIM from the site. Can this be useful tome understanding the HAL layer along...
Hey folks, I am working on a project where our cost and sizeare creeping up and some of our management are startingto ask about whether or...
Hey folks, I am working on a project where our cost and sizeare creeping up and some of our management are startingto ask about whether or not we need to be consideringgoing to ASIC technology. Fortunately, our budget allowsus to consider this option. Since I have never been in charge of a project that designedits own chip, I have a few Q's that I hope the embeddedfolks can ...
Looking to identify an "ASIC" and find information on same.Known info is as follows:Motorola84pin PLCCCirca Mid-late 1980's2 MHz...
Looking to identify an "ASIC" and find information on same.Known info is as follows:Motorola84pin PLCCCirca Mid-late 1980's2 MHz clock rate (in one application)Marking line1 - M (Duh!)Marking line2 - S38FC049PIO3Marking line 3 - ZKZKAC9039Speculative information:This module was programmed locally.Any guesses? I can post a picture if it would...
Hi,I did a design with AT45DB321D to use with ASIC. the ASIC development kitcontained the AT45DB321D 32Mbit flash and I use the same thing in...
Hi,I did a design with AT45DB321D to use with ASIC. the ASIC development kitcontained the AT45DB321D 32Mbit flash and I use the same thing in mydesign.But now unfortunately the AT45DB321D 32Mbit chip is out of stock everywhere and it has 7 months lead time. is there any one who know a compatiblepart for this serial flash ---------------------------------------Posted t...
Hey folks , i need ur opinion about something :To implement an AES decryption (CBC mode ) algorithm in ASIC , whatwould be the best way to do...
Hey folks , i need ur opinion about something :To implement an AES decryption (CBC mode ) algorithm in ASIC , whatwould be the best way to do it ? i mean among these architectureswhich one do you choose and why :* Basic iterative architecture* Partial loop unrolling* full loop unrolling* Partia outer-round pipelining* Full outerround pipelining* Inner-round pipelining* Part...
Hi all,Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?In general, what would be the maximum I could...
Hi all,Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?In general, what would be the maximum I could fit, if cost is not a limitation? Why?Our need would be for a large number, but could be split into many independent banks if thatmakes things easier. For example, 1,000 independent banks of 100 MBytes each. Or another possible partition (again...
Hello all,Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?In general, what would be the maximum I...
Hello all,Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?In general, what would be the maximum I could fit, if cost is not a limitation? Why?Our need would be for a large number, but could be split into many independent banks if thatmakes things easier. For example, 1,000 independent banks of 100 MBytes each. Or another possible partition (ag...
Does anyone know if there is a dev kit available for an MPEG encoderASIC - preferably one thatI could connect to a real-time video source as...
Does anyone know if there is a dev kit available for an MPEG encoderASIC - preferably one thatI could connect to a real-time video source as input and connect to anFPGA board for post processing...In otherwords an MPEG ASIC dev kit with a lot of IO options.Also can anyone suggest a (separate, additional) dev kit that wouldsupport reading and riding to a hard disk, preferably one that...
There must be some reason....Can anybody post it here?
There must be some reason....Can anybody post it here?
Application Specific Standard Product(ASSP) Structured ASIC configurable processor I am not a IC design,but a embedded software...
Application Specific Standard Product(ASSP) Structured ASIC configurable processor I am not a IC design,but a embedded software engineer. A few newterms come to me and I have no idea. I can find plenty of informationon the internet, but none of them explains the terms.So can anyone give me an introductionary explanation and give oneexample each? thanx
Hi Experts,Let me start by providing some background.We have designed an ASIC: 8051 + non standard peripherals (timers etc)+ FLASH + RF...
Hi Experts,Let me start by providing some background.We have designed an ASIC: 8051 + non standard peripherals (timers etc)+ FLASH + RF frontent for a product used in wireless communications.The 8051 currently has a single breakpoint register, and we havemanaged to integrate with the Keil debugger (single stepping andbreakpoints seem to work OK)Anyway, we are now looking at t...
I am investigating possible hardware implementation of a router/packetclassifier in ASIC/FPGA. Where can I find the relevant information to...
I am investigating possible hardware implementation of a router/packetclassifier in ASIC/FPGA. Where can I find the relevant information to startwith. ---------------------------------------Posted through http://www.EmbeddedRelated.com
I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC...
I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC (LCD controller) or FPGA (VHDL core) design will do. Thanks,Damir
Hello !We are an academic institution teaching our students VLSI design, from FPGAto full custom ASIC. We have put great value on...
Hello !We are an academic institution teaching our students VLSI design, from FPGAto full custom ASIC. We have put great value on teaching VHDL during thepast years with very good results from our students.However, we have the impression that these students have difficultiesworking with schematics as tools to document and express theirarchitectural ideas, in part because we di...
hi,im a newbie in DSP and embedded programming and i've some doubts thati hope some of you could kindly answer.i've to do some profiling...
hi,im a newbie in DSP and embedded programming and i've some doubts thati hope some of you could kindly answer.i've to do some profiling between DSP and ASIC/FPGA solutions. Im aFPGA guy so im lost with this DSP thing.1)i'd like to know what do you think about the code i wrote, cause ifeel it's not very "DSP optimized". I need to implement some sort ofshiftregister or FIFO, b...
Hello,am New to PCB board design cycle. Working on circuit having powerPCinterfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do...
Hello,am New to PCB board design cycle. Working on circuit having powerPCinterfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do thecycle accurate Functional simulation of the above circuit.How should i go for it?Queries:1. Which tool i should use.2. Do i need to convert schematics into verilog?3. Do i need Models for all the components in the circuit. What is the p...
hi,im a newbie in DSP and embedded programming and i've some doubts thati hope some of you could kindly answer.i've to do some profiling...
hi,im a newbie in DSP and embedded programming and i've some doubts thati hope some of you could kindly answer.i've to do some profiling between DSP and ASIC/FPGA solutions. Im aFPGA guy so im lost with this DSP thing.1)i'd like to know what do you think about the code i wrote, cause ifeel it's not very "DSP optimized". I need to implement some sort ofshiftregister or FIFO, b...
Hello all,I'm working on the idea/presentation for my next book. It relates toretrogaming from an embedded developer's standpoint (not an...
Hello all,I'm working on the idea/presentation for my next book. It relates toretrogaming from an embedded developer's standpoint (not an emulationbook, but more along the lines of "this is how you could develop amodern version of the 2D tile-based graphics ASIC in XYZ old arcademachine", and "this is how you can simulate a YM2159 synthesizer inVHDL"). I feel many of these circuits h...
