NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.  The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.  NAND Flash devices have become a viable alternative in systems where read latency and data integrity are not critical device characteristics.  This paper describes NOR’s current trajectories and operational characteristics that will enable usage in future applications.

Process shrinks allow for extended product life cycles
Over the past decade the pace of density growth has continued at a remarkable rate (Figure 1).  Density growth will continue into the future.   In 2011 we will see the introduction of a 4Gb NOR device and the next generation process node (45nm) will be released to production in 2012.  Work has already begun on the follow-up node at 32nm to continue the process development roadmap.

FIGURE 1: Spansion’s NOR Flash Density Growth over the Last Ten Years

NOR manufacturers have historically been aggressive in applying new process technologies not only to the highest density devices but also to reduce the die sizes of lower density legacy products.  Spansion’s 65nm process is not only used for the highest density 2Gb (and upcoming 4Gb) products but is also being used to shrink products between 64Mb and 1Gb.  The smaller die sizes resulting from the continued application of new process nodes extends the length of time that a product remains commercially viable.  While the 1Mb Async NOR product (AM29F010B) referenced in Figure 2 uses an older process node (320nm), it should be noted that the device is compatible with the much older AMD AM29F010 that was released to production in 1992 (using an even older process node).  NOR’s extended product life cycle and breadth of available densities is unique in the memory industry.

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FIGURE 2: Available Densities of Candidate Memories

The longer product life cycles are also due to reduced pressure for a typical NOR application to migrate to the highest density node.  Overall, NOR’s wide range of applications have a much broader distribution of density usage than NAND applications.  NOR applications tend to vary widely in density requirements and migrate to the next higher density node rather than jumping to the highest density device.  The bulk of NOR applications do not migrate to a leading edge density as compared to NAND applications that tend to rapidly migrate toward the highest available device density.  NAND’s focus on leading edge densities often comes at the expense of lower density products (using older process nodes) that tend to become obsolete after relatively short life cycles.

Minimizing system level active signal count within the memory sub-system is important for a number of reasons.  

1. A lower active signal count memory can often be placed in a less expensive package.
2. PCB area and perhaps the number of PCB layers may be reduced when there are fewer traces to route.
3. A lower active signal count memory subsystem allows the host SoC to either reallocate pins for alternate purposes or to reduce overall pin count.
4. Lower active signal counts often allow memory manufacturers to test more devices simultaneously, which results in reduced testing costs.

Memory subsystem active signal count is minimized when both the volatile and non-volatile memories reside on the same bus.  Consolidated busses include the Parallel NOR bus (ADP – address data parallel) and the multiplexed NOR bus (ADM – address data multiplexed).  Note that the Burst ADM bus is the most attractive from a active signal count perspective (Table 1).  Shared ADP/ADM NOR buses often use PSRAM devices that have a cost advantage over PC-DRAM at lower densities.  At higher densities commodity PC-DRAM provide a lower cost volatile memory alternative.

PC-DRAM devices have interface characteristics that are incompatible with available non-volatile memories.  If a system is to take advantage of the low cost and high performance characteristics of higher density PC-DRAM products, a split bus approach is used with independent volatile and non-volatile memory buses.  This split bus approach results in a higher overall active signal count for the memory subsystem.  PC-DRAM based systems use a shadowing model where the content of the non-volatile memory is copied to DRAM either during the boot process or when needed during normal operation.  In these PC-DRAM based systems, execute in place functionality is not a requirement and a serial non-volatile memory interface (SPI NOR or NAND) becomes attractive from a active signal count perspective.  In this split bus implementation the non-volatile SPI bus provides the lowest overall active signal count (Table 1).

TABLE 1: System Level Signal Count of Memory Combinations (Volatile + Nonvolatile) . Click image to download larger version.

NOR’s system responsiveness essential in many applications
System responsiveness is largely dependent on the memory subsystem’s initial latency and bus throughput.  NOR devices have significantly shorter initial access times than NAND products (Figure 3).  NOR’s initial access time advantage is up to 250x when compared to SLC NAND (100ns vs. 25us) and up to 750x for MLC NAND (100ns vs. 75us).  The advantage that NOR has over NAND is compounded when the virtual to physical address translation that is required in most NAND implementations is considered.  In particular, the Managed NAND usage model stores the virtual to physical translation table in the NAND device and requires one or more additional read operations to identify the physical address of the desired target data.  NOR based implementations often use a direct mapping of data where a virtual to physical translation is not required.

FIGURE 3: Initial Latencies

Throughput is dependent on several factors, including: how fast data can be transmitted and received on each data signal, the data bus width, and how effectively the memory device can pipeline accesses (Figure 4).  PC-DRAM and LP-DRAM (LPDDRx) devices combine a low latency array structure, a high-speed signaling interface and the ability to pipeline read/write accesses.  NOR devices have higher bus throughputs than legacy NAND products.  While a DDR interface has been developed for NAND products, penetration into the embedded world has not yet become widespread.
 
NOR’s short initial latency and competitive bus rates allow for direct code execution as well as low latency data storage.  This combination (low latency, high bus rates) is NOR’s fundamental technical value proposition that remains relevant, even after over 20 years of market acceptance.

FIGURE 4: Throughput on Each Data Bus Signal

One usage model that has emerged is the storage of graphics data in NOR devices as a strategy to reduce or eliminate the need for a large SRAM or DRAM based graphics buffer.  In this scenario the host system is constantly pulling small amounts of data from a NOR device to “feed” a graphics controller.  The transfer size varies but a large portion of the transfers are on the order of 64-256B.  Figure 5 is a throughput comparison of a NOR and NAND based approach to this usage scenario.  The comparison assumes the following:

• 128B transfers
• 100ns NOR initial latency
• 25us SLC NAND initial latency
• 100MHz NOR bus rate (16b bus)
• 50MHz NAND bus rate (8b bus)
• NAND requires 1 additional read to perform a virtual to physical address translation

The 71x advantage that the NOR device has over NAND is largely due to the dramatically shorter initial latency (100ns vs. 25us).  NAND would not be an attractive choice for this usage scenario where the graphics data needs to reside directly in a low latency memory.  A NAND based solution would typically be implemented with the addition of a (DRAM) volatile memory  device where the relevant graphics data would be shadowed.  The low latency characteristics of the additional DRAM device would be able to achieve the throughputs required by this application.

 
FIGURE 5: Responsiveness NOR vs. NAND?NOR Flash completes 71 128B transfers while NAND completes its first.

Another emerging NOR usage scenario is the proliferation of low pin count SPI NOR Flash devices as the only non-volatile memory in the system.  These SPI devices are available with a four-bit data bus running at clock rates above 100MHz.  To further increase bus throughput some SPI NOR manufacturers have introduced DDR variants.  SPI NOR devices have historically been used in systems that shadow the NVM contents into SDRAM for code execution.  With the relatively high data rates and low latencies of SPI NOR Flash devices, host chipsets are able to perform code execution out of the SPI device.  This direct code execution out of a low cost serial memory is a trend that will continue to proliferate.

Conclusion
Engineers will gravitate toward the lowest cost solution as long as the targeted system level performance is attained.  The memory selection process is often complex because the preferred chipset does not support all possible volatile and non-volatile memory pairings.   Low and mid density NOR/PSRAM pairings will be attractive in many applications because of low pin count and low cost.  At higher densities, NOR Flash will continue to be attractive when low latency and high read throughputs are critical design criterion.

A continuing trend in NOR Flash evolution will be the balancing of pin count and bus read throughput.  SPI devices in particular have increased both operating frequencies and data bus throughput without increasing the signal count of the legacy interface.  SPI offerings are starting to appear that include a DDR bus protocol, significantly improving read performance.  SPI NOR and parallel NOR offerings are approaching inherent protocol constraints that will limit further increases in bus throughput.  Next generation NOR products will increasingly adopt the high speed interface strategies common in the DRAM world to continue improving read throughputs while keeping overall active signal count to a minimum.

In conclusion, NOR Flash will continue to offer performance and longevity advantages for the embedded landscape (from automotive, telnet, consumer to gaming to industrial applications) with low pin count interfaces, long product life cycles and superior read performance.

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