Samsung Confirms 24 Layers in 3D NAND
Samsung was a bit economical with the engineering details when it announced its128Gbit multilayered NAND flash memory this week. The company did not mention how many layers are used in the device or what geometry process technology is used to make it. However, a Samsung spokesperson who responded to our email questions has allowed us to fill in some details and invoke hand-waving arguments about others.
Samsung did say in its press release that the technology can stack “as many as 24 cell layers.” Through email, the company confirmed that this first vertical NAND flash memory is a 24-layered device, and that it is being manufactured at Hwaseong, South Korea.
The spokesperson would not answer questions about the manufacturing process geometry for the 128Gbit vertical NAND or whether the charge-trap technology is capable of multi-level cell (MLC) operation. But the company did say the die area is approximately the same as that for a 2D NAND flash memory made using mid-10nm-class process technology.
As far as I know, Samsung has both 64Gbit and 128Gbit 2D NAND flash memories being manufactured in 1X nm process technology. The128Gbit 2D NAND device was announced in April. If we make a couple of assumptions, this should allow a little more light to be shed on the vertical NAND. Let us assume that the die area of the 128Gbit V-NAND flash memory is the same as for the 128Gbit 2D NAND flash introduced by Samsung April on 1X-nm class manufacturing process. Let us also assume that MLC has not been deployed in the V-NAND flash.
Since the 2D NAND used three-bit MLC memory, it follows that the V-NAND memory must have three times as many memory cells spread across 24 layers. This means that the memory cell density per layer of the V-NAND memory can be lower than that for the 2D NAND memory by a factor of eight. Area varies with the square of linear geometry. Therefore, it follows that the V-NAND could be up to about 2.8 times more relaxed in its minimum geometry than the 2D NAND.
These are coarse approximations, because parts of the V-NAND die area may be given over to additional addressing circuitry to cope with multiple layers or for through-silicon vias that might be used later for a stacked die arrangement. But putting those uncertainties to one side, if the 128Gbit 2D NAND were made using a 16nm minimum geometry manufacturing process technology, then it seems a V-NAND memory of the same capacity and die area would require only about 45nm of minimum geometry.
This jump back multiple manufacturing process generations could have significant benefits in terms of getting extended use out of amortized equipment and wafer fabs, resulting in reduced costs. Of course, there is the extra cost and yield-limiting effect of lining up and connecting 24 layers.
What is most striking and slightly worrying is that Samsung said in its press release that the technology is capable of up to 24 layers. If that remains the case, vertical NANDa la Samsung would provide a one-time benefit only.
The industry expectation is that vertical NAND can scale in terms of the number of layers and allow the industry to jump back to easier-to-produce manufacturing nodes, where more electrons are stored and cycling endurance and reliability are higher and better understood. As the first company into the market with vertical NAND, Samsung looks set to be the pathfinder for how far that vertical scaling can go.
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Industry veteran Peter Clarke runs EETimes Europe's Analog website. With special interests in emerging technology and startups, he's been writing about the semiconductor industry since 1984 and wrote for EE Times US from 1994 to 2013.
Nice job digging deeper into his vertical and somewhat foggy territory, Peter!
I understand Samsung will present at next week's Flash Summit in San Jose and I am trying to get a look sat foils to see if they will add anything to this discussion.
Meanwhile I wonder, what is the interest level in this topic in the community? Do you have specific questions about this technology? Do you care HOW it works or only that it has X, Y and Z specs and costs?
I will ask the same questions I had earlier asked @Peter.
Per some blog Samsung is supposed to stack 8 of these 3-d NAND chips and sell them as a 128GB module. That blog claimed that the 8 chips will use TSVs for vertical interconnect. Perhaps Peter will soon have an answer from Samsung, if not could @Rick pl. ask Samsung about it at the Flash summit in SJ ?
I agree with Peter's assessment. If 24 is the max, they could start SLC then go to MLC then TLC. Otherwise they'd be expected to do 48 layers next, then 96, etc. It might mean they start RRAM in 2017-2019 time frame.
As is well-known, in the charge-trap FLASH, an ONO triple-layer is used as a memory layer. For the V-NAND FLASH, the ONO layer is formed to cover an inner surface of a hole vertically penetrating word-line layers. Since the thickness of the ONO layer cannot be shrunk, the penetrating hole should be larger than, at least, twice of the thickness of the ONO layer. In addition, a polysilicon layer serving as a channel should be formed in the penetrating hole. This means that the design rule of the V-NAND should be larger than 50 nm. Owing to this, Samsung emphasized that there is no need for EUV.
These facts were explained by Macronix, in order to stress technical advantages of their VG-NAND type FLASH over Samsung's TCAT or Toshiba's BiCS.
http://www.sematech.org/meetings/archives/symposia/9027/pres/Session%203/Lue_HangTing.pdf (See P. 31)
In conclusion, your answer of about 45nm seems to be right. However, it is uncertain whether the assumptions are right. This is because each nand string of 2D FLASH is realized on a xy plane parallel to the wafer but that of 3D V-NAND is realized on a xz or yz plane. In other words, to answer your question, additional information (e.g., on a 2D area of unit cell of 3D V-NAND) should be provided. I think that the number of the penetrating holes is directly related to this information. (Although I can't remember the exact site, I read that somewhere.)
In the meantime, 3D RRAM may be superior to V-NAND FLASH. However, it should be emphasized that V-NAND FLASH is already in production stage. It seems that 3D RRAM is still in developing stage.
Can any reader answer whether Samsung TCAT is capable of MLC?
Feels like Micron (and others) will start to move 3D-NAND up now Samsung is in the field
This from a spokesperson for Samsung.
"Samsung is not under consideration of applying through silicon vias in creating 3D V-NAND packages at this moment."
This from a spokesperson for Samsung.
"Samsung is not under consideration of applying through silicon vias in creating 3D V-NAND packages at this moment."
@Peter : Thank you for your effort. Had suspected the same myself based on current status of 3D TSV technology. But the Blogosphere cannot be totally dismissed either.
If the technology were not at least theoretically capable of MLC, it might be hard to push. Extending vertically might be only way otherwise. It might make MLC harder by reducing read current. And there could be retention issues since there is no opportunity to confine charge vertically.
Seems SK Hynix had given indication of things to come a few months ago.
Engadget reports Samsung is targeting V-NAND for enterprise SSDs, so it's being positioned as an expensive NAND not the obvious lower cost per bit choice.
There is some extra cost for requiring double patterning even at the looser design rule. And there are many layers to be deposited and etched which in total far exceed the material consumption by quadruple patterning. I think all that is reduced dramatically is exposure cost but they're adding new layers and are they really patterning all the 24 layers in one shot (how thick photoresist?).
I doubt they are patterning the layers in one shot.
I am sure it is an interative process building up the layers
And then punch through with connecting via.
So I think you are right if you are implying much longer dwell-time on the exposure and etch machines to end up with 24 layers but only the same memory capacity.
But the masks are cheaper in older technology...and in theory this may scale to say 96 layers providing a memory density otherwise unachievable.
That's a good point. Microloading or insufficient resist thickness can limit the etch depth, and therefore the number of layers. But iterating cannot reduce the cost per bit.
They also said 24 layers, not 24 storage layers. This could mean that memory storage is only 12 layers with passivating layers between. They could be counting all the layers to total the 24.
I think we can also assume this is MLC. They claimed 35k write cycles on this and how it had 2-10X better reliability than existing NAND. Assuming this is in reference to cycling, SLC can already exceed 35k cycles.
@rage33: it's a good consideration. Although in the TCAT the gate dielectric layers are wrapped around the gate, it may not be simple alternating of two layers.
There was a followup statement by Samsung which confirmed they were using MLC, but the 24 layers probably should be taken to mean device layers. Because in the statement they emphasized the desire to go beyond the 10 nm equivalent density. This would be possible with both MLC and 24 device layers.
http://www.theregister.co.uk/2013/08/19/samsung_launches_damp_3d_ssd_squib/
But they achieve this goal at very high cost. It appears necessary they need to do at least one process sequence iteration. Thus it is targeted for enterprise rather than consumer.
http://www.engadget.com/2013/08/13/samsung-unveils-first-ssds-with-3d-v-nand-memory/
The latter announcement at engadget also confirms the 24 layers as device layers.
The following figure shows there was no iteration.
http://techon.nikkeibp.co.jp/english/NEWS_EN/20130820/298329/?SS=imgview_e&FD=48575398&ad_q
Not so sure about that. Check the narrowest line positions has some discontinuity. But need a better view to confirm.
Thanks for pursuing the details. But for sure each of the 24 layers has its own iteration of mask redeposition (to prevent hole widening), nitride etch, and oxide etch. If applied to spacer pitch division, the pitch would have been divided by 2^24, or almost 17 million, yet for 24 layer 3D NAND, it's only effectively divided by about 5. That's the cost efficiency gap.
Etching 24 pairs of alternating layers without deposition would be sufficient for pitch/24, in alternate spacer schemes.
If it exceeds 64 layers, that would be a longer than standard string length that degrades performance. So not much leg here.
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