Intel outlines road to McKinley processor
SAN JOSE, Calif Intel Corp. has outlined its battle plan for the high-end workstation and server market, long a difficult area for the company.
Intel will launch Merced and its successor microprocessors at the high end, but Intel has been concurrently developing a processor family, code-named Foster, that will provide a hedge for mainstream servers and workstations, Intel officials revealed.
In addition to describing its plans for Merced's IA-64 architecture, Intel spelled out the future of the Pentium II Xeon family. It will be transformed into a new architecture that will debut in 2001 with the Foster and Wilamette processors.
Intel is sending a message that “for the next couple of years, even past the debut of Merced, IA-32 will be the important architecture except for the very high end,” said Michael Slater, executive editor ofMicroprocessor Report .
Intel is talking to OEMs about its high-end MPU road map through 2002, details of which will be presented at Microprocessor Forum next week.
Merced remains on target for sampling next year, said Fred Pollack, a director with Intel's microprocessor products group. Meanwhile, Intel is working on an improved IA-64 part called McKinley, which is due to succeed Merced by 15 to 18 months.
Both of those chips will target the high end of the workstation and server markets.
In the mainstream market, the Pentium II Xeon will be succeeded by chips called Tanner and Cascades. But Intel hopes to replace those parts by 2001 with a new 32-bit architecture based on the X86 instruction set. That architecture will debut with Wilamette for the PC market and with Foster for the mainstream workstation and server market.
Merced will still be in a rather experimental stage at that point, so “Foster is going to be a far, far more important part than Merced” in terms of units sold, Slater said.
Pollack disclosed few details of the new architecture. Intel will be adding stages to the pipeline to increase throughput, and is improving pipeline efficiency to prevent instruction “bubbles” from getting stuck. Efficiency improvements include the addition of an on-chip “trace cache” that will store entire instructions. This spares instructions from being decoded when called again.
Bus bandwidth is expected to reach 3 GHz with Foster, compared with a peak of around 800 MHz for current systems, Pollack said. More important, Foster and Merced will use the same bus to encourage the migration by OEMs from Foster to Merced. “They're trying to make it relatively easy to incorporate IA-64 into people's processing plans,” Slater said.
Foster will match Merced's performance on 32-bit applications, and will beat it on floating-point operations, Pollack said. Merced will shine in applications that exploit its 64-bit addressing, and at managing memory and I/O. The latter becomes a burden in multiprocessor machines, and is one reason Intel's processors have competed weakly at the high end.
The Colusa chip set, which will appear concurrent with Foster, will allow systems to run up to four processors. Other chip sets that will support as many as 32 processors are being developed for the Merced track, Pollack said.
In addition, server OEMs are working on the chip sets to support up to 32 IA-64 processors in a system.
As for Merced itself, the microarchitecture has “been done for some time,” Pollack said, and register-transfer-level validation is also complete. Merced is in physical layout, and Intel designers have begun looking at the chip's timing to hit their frequency targets.
Intel has produced a chip kernel that's bootable under certain flavors of Unix and under an early version of 64-bit Windows NT. Merced remains on its revised schedule for sampling in mid-1999 and for production roughly one year later, Pollack said.
The previously undisclosed 64-bit McKinley chip, already two years into development, will include what Pollack called “lessons” improvements that couldn't be implemented in Merced without disrupting the entire design. Pollack declined to reveal frequency targets for Merced but said they will be less than the gigahertz-level target set for McKinley.
Under this road map, Merced will act as preamble to McKlinley, which is likely to debut in late 2001.
“McKinley is going to be a more interesting processor than Merced,” Slater said. “There'll be [at first] systems with Merced built in modest volumes. You'll see Merced as the chip that gets the architecture started.” But because companies such as Hewlett-Packard Co. and IBM Corp. seem comfortable with existing workstation and server processors, they won't shift to Merced immediately. That will put the processor “at the fringe of the market” in its early runs, Slater said.
By 2002, Intel hopes to have McKinley and Merced ported to 0.13 micron rules. That will add performance to the high end, but it will also lower costs and could allow the IA-64 parts to attack high-volume markets. By then, a larger share of workstation and server vendors may be ready to shift to a new processor architecture, Slater said.
“Realistically, it's going to be years before Merced or IA-64 processors are as significant as even Alpha is today,” he said. “It's probably going to be 2002 before they get there, which is a long time in this business.”
For that reason, it's difficult to pin a systems road map on Merced.
“The real issue is what happens with McKinley and its successors,” Slater said. “There's so much that could happen between here and there, it's a tough environment to make decisions in. Some work will be waiting for McKinley.
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