Using FPGAs to prototype and test complex SoCs is usually the most effective approach, and Cadence puts two to eight Virtex-7 chips under the hood of its new Protium system.

Protium is compatible with Cadence's Palladium platform flow, and supports up to 100 million gate capacity and the IEEE 1801 low-power standard.

This product is featured in EDN's Hot 100 products of 2014. See all 100here.

Even with all this horsepower, effort is still required to achieve reasonable emulation speed. With no user intervention, the effective clock rate may be as low as 3MHz, but can climb to 30MHz with manual guidance, and up to 100MHz with further tweaking.

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Connections to the outside world are provided by two 150-pin daughtercard connectors per FPGA.

Protium rapid prototyping platform

Cadence,www.cadence.com

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