Accommodation & Travel

Travel - Public Transport

As part of the major infrastructure projects linked to the creation of additional tramway lines, SYTRAL is undertaking major works in the first half of 2025 that will have an impact onRHONEXPRESS operations (express shuttle from the airport).

These disruptions will result in significant service changes, including partial or complete suspensions of the line.

Here's what you need to know:https://www.rhonexpress.fr/en_GB/perturbation

SpecialDATE 2025 delegate hotel room rates, airline fares & city card fees

  • In cooperation with the TCH - Top Conference Hotels and hotels in Lyon, the Conference Organisation can offer hotel rooms at favourable rates in Lyon for all conference delegates.
  • The Lufthansa Group airlines bring people together - every day, all around the world. The global route network of Austrian Airlines, Lufthansa, SWISS, Brussels Airlines and Eurowings offers optimal connection and combination options, so you will benefit from quick and direct flights to the event.
  • In cooperation with Visiter Lyon, the Conference Organisation can offer a discount on the Lyon City Card for all conference delegates.

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Authors' Guidelines for Camera-Ready Submission of Accepted Papers

Deadline:Friday, 17 January 2025 AoE

Your submission forDATE 2025 has been accepted. Congratulations!

This page contains instructions to prepare the final material required to publish your contribution in time for the conference.

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Sponsor Societies

Association for Computing Machinery - Special Interest Group on Design Automation (ACM SIGDA)Electronic System Design (ESD) AllianceEuropean Design and Automation Association (EDAA)IEEE Council on Electronic Design Automation (IEEE CEDA)

Technical Co-Sponsor Societies

IEEE Computer SocietyIEEE Computer Society Test Technology Technical Community (TTTC)IEEE Solid-State Circuits Society (IEEE SSCS)

Media Partners

3D & Systems SummitDACAsia and South Pacific Design Automation Conference (ASP-DAC)AUTOCAD MagazineEDACafe.comISS_LogoICCAD 2025MEMS & Imaging Sensors SummitSEMICON Europa

Sister Events

DACAsia and South Pacific Design Automation Conference (ASP-DAC)ICCAD 2025

Gold Sponsors

Chipdesign Germany (CDG)

Platinum Sponsors

Cadence Design SystemsIEEE Council on Electronic Design Automation (IEEE CEDA) Synopsys

Sponsors

Arm technologyCEACentrale LyonINSIDE Industry AssociationIROC TechnologiesPEPRRacyics GmbH

Registration & Participation

The online registration to the conference is only possible via the online registration platform which is available until2 April 2025. Please kindly note that everyone who wants to attend the conference or single sessions, must create an account and register, with which you can check your registration or make additional programme bookings later. If you participated inDATE 2024 in Valencia, Spain, please use the same login data.

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EDAA Achievement Award 2025 goes to Subhasish Mitra

Subhasish MitraThe Achievement Award is given to individuals who made outstanding contributions to the state of the art in electronic design, automation and testing of electronic systems in their life. To be eligible, candidates must have made innovative contributions that impacted how electronic systems are being designed.

Past recipients have been Kurt ANTREICH (2003), Hugo DE MAN (2004), Jochen JESS (2005), Robert BRAYTON (2006), Tom W. WILLIAMS (2007), Ernest S. KUH (2008), Jan M. RABAEY (2009), Daniel D. GAJSKI (2010), Melvin A. BREUER (2011), Alberto L. SANGIOVANNI-VINCENTELLI (2012), Peter MARWEDEL (2013), Rolf ERNST (2014), Lothar THIELE (2015), Giovanni DE MICHELI (2016), C. L. David LIU (2017), Mary Jane IRWIN (2018), Jacob ABRAHAM (2019), Luca BENINI (2020), Georges GIELEN (2021), Edward A. LEE (2022), Jason Cong (2023), and Ingrid Verbauwhede (2024).

Subhasish Mitra holds the William E. Ayer Endowed Chair Professorship in the Departments of Electrical Engineering and Computer Science at Stanford University. He directs the Stanford Robust Systems Group, serves on the leadership team of the Microelectronics Commons AI Hardware Hub funded by the US CHIPS and Science Act, leads the Computation Focus Area of the Stanford SystemX Alliance, and is the Associate Chair (Faculty Affairs) of Stanford Computer Science. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-Leti in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Merck (EMD Electronics), Samsung, and Xilinx (now AMD).

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EDAA Outstanding Dissertations Award 2025

https://www.edaa.com/awards/

EDAA is a non-profit association. Its purpose is to operate for educational, scientific and technical purposes for the benefit of the international electronics design and design automation community. The Association, in the field of design and design automation of electronic circuits and systems, promotes a series of high quality technical international conferences and workshops across Europe and cooperates actively to maintain harmonious relationships with other national and international technical societies and groups promoting the purpose of the Association. EDAA is the main sponsor of DATE, the premier Design, Automation and Test Conference in Europe.

EDAA Outstanding Dissertations Award 2025

In recognition of the importance of university research to the advancement of design, automation and test, and to encourage young researchers to work in the field, EDAA has established an award for outstanding Ph.D. dissertations in 4 categories:

  • Topic 1 – New directions in systems design methods and tools, simulation and validation, embedded software design and optimization for embedded, cyber-physical, secure and learning systems
  • Topic 2 – New directions in system-on-chip platforms co-design, novel architectures for future computing in design flows, and power management.
  • Topic 3 – New directions in logic, physical design and CAD for analog/mixed-signal, nanoscale and emerging technologies (such as quantum-, neuromorphic- or biological computing).
  • Topic 4 – New directions in safety, reliability, security-aware hardware design, validation and test

In each category, one award can be given. Each award consists of a 1000 € prize and certificate. The awards will be presented at theDATE 2025 conference, where the awardees need to be present.

Nomination

Eligible are all Ph.D. dissertations which have been defended in the last 2 years before the submission deadline. The total reporting time should not be more than 6 years since the starting of the PhD that should clearly be stated in the applicant CV.

The nominations must be submitted electronically, exclusively in PDF format, through the following URL address:http://www.edaa.com/awards Details for the nomination PDF can be found in the call linked below.

Nomination deadline is 13 December 2024 at midnight (AOE).

Award Chair

Ian O'Connor, Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France, and EDAA Vice-Chair Email:ian [dot]oconnoratec-lyon [dot]fr

Download the detailed call for nominations here:https://www.edaa.com/wp-content/uploads/2024/10/EDAA_OutstandingDissert…

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EDAA Achievement Award 2025

https://www.edaa.com/awards/

EDAA is a non-profit association. Its purpose is to operate for educational, scientific and technical purposes for the benefit of the international electronics design and design automation community. The Association, in the field of design and design automation of electronic circuits and systems, promotes a series of high quality technical international conferences and workshops across Europe and cooperates actively to maintain harmonious relationships with other national and international technical societies and groups promoting the purpose of the Association. EDAA is the main sponsor of DATE, the premier Design, Automation and Test Conference in Europe.

EDAA Achievement Award 2025

In 2025, the European Design and Automation Association (EDAA) will grant the 23rd EDAA Achievement Award.

Scope and Goals

The EDAA Achievement Award shall be given to individuals who made outstanding contributions to the state of the art in electronic design, electronic design automation, testing of electronic systems as well as embedded systems and software, during their career.

Candidates can be of any age. In order to be eligible, candidates must have made innovative contributions which had an impact on the way electronic and embedded systems are being designed. The goal of granting the award is to make the excellent work accomplish by people working within the above scope more widely known and to help publicizing the results more broadly.

Nomination

Nominations should be sent to the Chair of EDAA, Robert Wille (robert [dot]willeattum [dot]de), by 15 December 2024. Nominations should include a 2-/3-page appraisal of the candidate's work.

The award will be handed over during theDATE 2025 opening ceremony in Lyon, France.

Download the detailed call for nominations here:https://www.edaa.com/wp-content/uploads/2024/11/EDAA_Achievement_Call-2…

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Promotion & Sponsorship

DATE 2025 offers numerous opportunities to get in contact with the DATE community and to advertise their novel solutions.

Download theDATE 2025 Promotion & Sponsorship Opportunities here

DATE 2025 is the perfect opportunity to present and communicate your technological and business capabilities to scientific, industrial and commercial audiences at one single European event. All companies, institutions, universities, initiatives and projects that are linked to DATE as promotion partners or sponsors benefit from the additional visibility of their corporate identity, their products, services, expertise and cause.

TheDATE 2025 promotion & sponsorship opportunities brochure gives you and idea of whatDATE 2025 can offer. Tailor-made packages can be arranged to suit your special requests. Feel free to contact us to discuss your needs and ideas.

We would be delighted to welcome you among our promotion partners and sponsors at DATE, and to welcome you in Lyon for an interesting programme and effective networking.

For more details, please contact the

Kathleen Schäfer, K.I.T. Group GmbH Dresden, DEConference Organisation | Sponsorship
Kathleen Schäfer, K.I.T. Group GmbH Dresden, DE
date@kitdresden.de

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Venue

Centre de Congrès de Lyon (CCC Lyon)
50 quai Charles e Gaulle
69006 Lyon
France
Website

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DATE 2025 - Call for Papers

The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well as embedded software.

The three-day event consists of a conference with regular papers, late breaking results papers and extended abstracts, complemented by timely keynotes, special days, focus sessions, embedded tutorials, half-day workshops and multi-partner project sessions. The event will also host the Young People Programme and unplugged sessions fostering the networking and the exchange of information on relevant issues, recent research outcomes and career opportunities.

DATE 2025 is the 28th edition of an event that has always been the place for researchers, young professionals and industrial partners to meet, present their research and discuss the current development and next trends, with high emphasis on social interaction.

AtDATE 2025, the DATE community, again, comes together for the conference in an intensive three-day format, focussing on interaction as well as further strengthening the community. The vast majority of regular papers will be presented in technical sessions using short flash-presentations, where the emphasis is on poster-supported live interactions (in addition to the common full-length presentation videos available before, during and after the conference). By this, we continue to focus on the core value of conferences: meeting, discussing and exchanging.

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Keynotes

OK01 Opening Keynote: Towards greener electronics and a 1000x gain in energy efficiency: co-optimizing innovative IC architectures, disruptive CMOS technologies and new EDA tools.

Start

Semiconductors and chips are ever-present in our current digital world. From smart sensors and the industrial Internet of Things to Digital Cities, personalized Medecine, Precision Agriculture, Vehicle Automation, and Cloud & High Performance Computing, semiconductor applications cover a very wide spectrum of society’s needs. However, global warming is highlighting the social and environmental impact of the digital transition, and the complex trade-offs and choices that lie ahead if we are to build a sustainable world. How do we pursue digitalization taking into account a limited power budget and the planetary limits? How do we make greener choices in the face of ever-increasing/aggressive competition? How do we choose the right digital performance for each application instead of a one-size-fits-all scenario, with a best performance for all approach? The semiconductor ecosystem is indeed facing a difficult dilemma with complex key tradeoffs.

With these stakes clearly in mind, the semiconductor community is performing disruptive research to provide greener electronics, able to attain very large gains in energy efficiency and just the right performance for each application. With the help of AI-boosted design methodologies and CAD tools, we have set out to co-optimize innovative CMOS technologies, disruptive chip architectures, computing models with new algorithms for embedded software.

This paper will provide an overview of the global semiconductor landscape and the challenge of mastering the data deluge for the entire semiconductor ecosystem. In order to face this challenge, we must all work together to reduce the collection, transport and storage of fruitless data.

This keynote will spend some time describing recent results from CEA-Leti and CEA-List’s research on sustainable and greener technologies.

To conclude, I will present an overview of the European Chips Act initiative, with the launch of the pilot lines, the Design Platforms and Competence Centers, a pan-European program that will be driving key milestones in the next five years to accelerate the accomplishment of our common goal of a sustainable and sovereign digital Europe.

OK02 Opening Keynote: A Vision of Systems and Technology in a Connected Europe

Start

The unprecedented growth of electronic system applications, from AI to smart products, creates both a huge market opportunity and a deep need for talented engineers. Europe will play a dominant role in the thirties if we (i.e., our community) can set up the premises for such a technology expansion now. Whereas the European Chip Act is an important enabler, finance represents only one of the necessary conditions for success. The key aspect is the ability to leverage diverse competences and connect the partially-untapped energies of the various European players, ranging from Industry to Academia.

Europe’s strength stems from diversity and the ability to design complex systems from parts, possibly coming from various sources. The ‘value added’ comes from the engineers who can create functionality and services, and who can adapt it to a diverse market of consumers. Yet I argue that this precious resource, the human capital represented by engineers and technologists, is too scarce and its limitation in size is a main handicap for creating a strong market of intelligent products and services. Education of engineers has to evolve and concentrate on the broader issue of system problem solving based on a deep understanding of technology. Industry has to join forces with academia by sharing knowledge and objectives and by creating a strong enthusiasm for engineering.

LK01 IEEE CEDA Lunchtime Panel: on the occasion of CEDA 20th anniversary

Start
Abstract


Session chair:
Georges Gielen, KU Leuven, BE

Speakers:
Rolf Ernst, TU Braunschweig, DE; David Atienza, École Polytechnique Fédérale de Lausanne (EPFL), CH; Valeria Bertacco, University of Michigan, US; Luca Benini, ETH Zurich, CH | Università di Bologna, IT

In celebration of IEEE CEDA’s 20th anniversary, this panel discusses the role of electronic design automation (EDA) in designing today’s multi-billion-transistor chips. With CMOS technology scaling approaching the range of a few nanometer and chips going 3D, what design techniques and tools will be needed to design these future integrated systems? Or will other technologies pop up and dominate? Where are the challenges? Who will provide the solutions? Will it be open source?

Join us for this special IEEE CEDA anniversary panel to discuss these questions and share your insights.

LK02 ASD Lunchtime Keynote: AI/ML at the Forefront of Semiconductor Evolution: Enhancing Design, Efficiency, and Performance

Start

As artificial intelligence (AI) and machine learning (ML) drive innovation, their impact on the semiconductor market is transformative. This keynote will explore the latest AI/ML trends and their implications for SoC designs targeting high-performance compute, edge AI, and IoT applications. The presentation will cover AI/ML's role in developing next-generation semiconductor designs, including how AI/ML algorithms are incorporated into EDA tools to optimize chip design and enable efficient verification and manufacturing. Emerging AI/ML trends driving requirements for advanced neural processing units (NPU) will be explored, including generative AI applications like large language models and text-to-image generators. Finally, the role of transformer-based neural networks in implementing energy-efficient SoCs will be discussed.

LK03 Special Day Emerging Computing Paradigm Lunchtime Keynote: Neuromorphic Computing at Cloud Level

Start

AI is having an increasingly large impact on our daily lives. However, current AI hardware and algorithms are still only partially inspired by the major blueprint for AI, i.e. the human brain. In particular, even the best AI hardware is still far away from the 20W power consumption, the low latency and the unprecedented large scale, high-throughput processing offered by the human brain.

In this talk, I will describe our bio-inspired AI hardware, in particular our award-winning SpiNNaker2 system, which achieves a unique fusion of GPU, CPU, neuromorphic and probabilistic components. It takes inspiration from biology not just at the single-neuron level like current neuromorphic chips, but throughout all architectural levels.

On the algorithm front, I will give examples on how to use general neurobiological computing principles (hierarchy, asynchronity, dynamic sparsity and distance-dependent topologies/hierarchical computing) to reframe conventional AI algorithms, usually achieving an order of magnitude improvement in energy-delay product.

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