Versal AI Engines: Meeting the High Performance DSP Compute Demands of Next-Generation Applications

In many dynamic and evolving DSP markets such as aerospace, defense, automotive/industrial, & test/measurement; applications are pushing for ever increasing DSP compute acceleration while remaining power efficient. 

With Moore's Law and Dennard Scaling no longer following their traditional trajectory, moving to the next-generation silicon node alone cannot deliver the benefits of lower power and cost with better performance, as in previous generations.

Responding to this non-linear increase in demand by next-generation DSP applications, like polyphase channelization and beamforming, AMD has developed a new innovative processing technology, the AI Engine, as part of the AMD Versal™ architecture.

A Closer Look at Versal AI Engines:

AI Engine Architecture

AI Engines are architected as 2D arrays consisting of multiple AI Engine tiles and allow for a very scalable solution across the Versal portfolio, ranging from 10s to 100s of AI Engines in a single device, servicing the compute needs of a breadth of applications. 

Benefits include:

Software Programmability

• C programmable via the Vitis Unified Software Platform
• Model-Based programming via Vits Model Composer 
• Learn more about the AI Engine DSP Design Process 

Deterministic

• Dedicated instruction and data memories
• Dedicated connectivity paired with DMA engines for scheduled data movement using connectivity between AI Engine tiles 

Efficiency

• Delivers increased DSP compute density when compared with traditional programmable logic, while reducing dynamic power consumption. Clickhere to learn more. 

Based on an ASIC-class architecture, AMD adaptive SoCs and FPGAs combine multi-hundred giga-bit-per-second I/O bandwidth with over 49 TeraMACs of fixed point DSP performance in the Versal™ Premium series. The AMD DSP slice and its parallelism is key to the achievable DSP performance in the latest generation of AMD FPGAs.

DSP Slice Architecture

The DSP58 in Versal devices slice is the 6th generation of DSP slices in AMD architectures.

This dedicated DSP processing block is implemented in full custom silicon that delivers leading power/performance allowing efficient implementations of popular DSP functions, such as a multiply-accumulator (MACC), multiply-adder (MADD) or complex multiply.

The slice also provides capabilities to perform different kinds of logic operations, such as AND, OR and XOR operations.

The Versal device DSP58 architecture builds on the success of the UltraScale™ FPGA DSP48E2 with further enhancements:

• Wider multiplier (27 x 24 bits)
• Single-precision, floating-point multiplier
  
• 18x18 complex multiplication using two back-to-back DSPs
  
• INT8 vector dot product mode
  

These enhancements help DSP critical applications perform more computation within the DSP48E2 slice before going into the FPGA fabric, ultimately leading to both resource and power savings.

DSP48E2 (UltraScale) vs DSP58 (Versal) Slice Features

Function	UltraScale	Versal
DSP Tile/Slice Type	DSP48E2	DSP58
Multiple Add/Sub/Acc operations
Multiplier and MACC	27x18	27x24
Squaring:  [(A or B) +/- D]2
WMUX Feedback Ultra Efficient Complex Multiply CMACC	3 x DSP48E2	2 x DSP58
SIMD Support
Integrated Pattern Detect Circuitry
Integrated Logic Unit
Wide Mux Functions	48-bit	58-bit
Wide XOR	96-bit	116-bit
Single Precision Floating Point Multiplier
Optional 96-bit Output
Cascade Routing
Pipeline Registers
D Pre-adder
Sequential Complex Multiply, AB dyn access
AB Register Pipeline Balancing Improved

Featured Videos:

1. Utilizing the Squaring MUX in the DSP48E2 slice (Video)
2. Utilizing the Wide MUX Feedback in the DSP48E2 slice (Video)

Tools and Flows

Depending on your designing preferences, AMD has tools supporting RTL, C/C++ and model-based design entry. This flexibility in the design flow, along with an extensive DSP IP catalog, facilitates easier adoption of AMD tools and devices.

Visit Tools, Libraries & Frameworks for more information.

DSP Performance Metrics

The following table shows some of the key DSP performance metrics for 7  Series, UltraScale™ and UltraScale+™ families. For adaptive SoC device performance, see Software Developer section.

We have introduced software development environments and a comprehensive set of familiar and powerful tools, libraries and methodologies which allow software developers to target AMD adaptive SoCs and FPGAs with ease. With high level abstraction environment Vitis™ unified software platform. We can offer GPU-like and familiar embedded application development and runtime experiences for C, C++ and/or OpenCL development.

AMD MPSoCs and Versal Devices

The Zynq™ UltraScale+™ MPSoC and the Versal architecture combine a powerful processing system (PS), incorporating Arm® Cortex® processors, and user-programmable logic (PL), in a single device.

Application Profiling for Acceleration

The Vitis unified software platform provides the ability to profile a given application and allows for the creation of hardware accelerators to run more efficiently in the Programmable Logic (PL), where the flexibility and parallelism of the FPGA are leveraged to provide large performance improvements. This also enables other functions of the application to run in the Processing System (PS) in parallel if desired.

By targeting AMD adaptive SoCs and FPGAs, many DSP and embedded applications will see improvements in efficiency and reduced power for their applications.

Features and DSP Performance of AMD SoC Devices

The following tables show some of the key features and DSP performance metrics for both AMD Zynq UltraScale+ MPSoC families and Versal™ devices. For non-SoC device performance, visit the Hardware Designer section.

Notes:

1. All performance calculations based of -2 speed grade parts for Zynq 7000 adaptive SoC and -3 for Zynq UltraScale+ MPSoC
2. Using the pre-adder DSP performance can be increased 2x for symmetric filters
3. Please refer to WP486 – Deep Learning with INT8 Optimization on AMD Devices (Not applicable for Zynq devices)
4. Single Precision Floating Point performance using Floating Point Operator core with 3 DSP slices
5. Single Precision Floating Point performance using Floating Point Operator core with 4 DSP slices
6.  Half Precision Floating Point performance using Floating Point Operator core with 2 DSP slices

To learn more about AMD adaptive SoCs and MPSoCs, go to:

• AMD adaptive SoCs & MPSoCs

DSP in the Processing Subsystem

The Processing System (PS) provides DSP processing capabilities by way of the different ARM processing cores.

For more information on DSP capabilities in the ARM processors, visit:

• Cortex-A Series Family
• SIMD and Advanced SIMD (NEON) technologies
• ARM Floating Point Architecture

Some useful examples can be found at the following locations:

For Zynq UltraScale+ MPSoC, see UG1211 for a demonstration of an FFT using the ARM NEON instruction set.

For Zynq 7000 SoC, the following Tech Tips are available on Xilinx wiki when targeting the Cortex-A9 and ARM SIMD:

• Building ARM NEON Library Tech Tip 2014.3
• Running ARM Library Tests Tech Tip 2014.3

AMD Data-type Support

AMD has very flexible data-type support in their devices. Varying precisions of Fixed Point, Floating Point and Integer are supported natively in AMD tools with Floating Point being implemented with the aid of the Floating Point Operator IP core.

Floating Point designs implemented on FPGAs will always lead to higher resource and power usage compared to Fixed Point or Integer implementations. Converting to a fixed point solution where possible will bring large benefits:

• Fewer FPGA resources
• Lower power
• Lower cost

For more details on the benefits of converting from floating point to fixed point data types, please read WP491.

Benchmarks

The below tables show a small selection of algorithms and possible performance improvements by using an AMD device and in particular the fabric in the programmable logic (PL) to accelerate the design.

Notes:

1. ARM: Quad-core A53 run on Raspberry Pi @ 1200MHz
2. Nvidia benchmarks were done using Tegra X1
3. Optical Flow (LK) – Window Size 11x1

Notes:

1. Cortex-A9 core used only on the Zynq devices when targeting ARM
2. TI benchmarks were done using C66 DSP core

AMD high-level design tools like Vitis Model Composer for DSP and High Level Synthesis provide a level of abstraction that empower system architects and domain experts to rapidly evaluate new algorithms and focus on developing the differentiating parts of their design. The complete AMD DSP solution is a combination of these design tools, IP, reference designs, methodologies and boards that work together to get to a working production design in the shortest time possible.

The Vitis Model Composer is a Model-Based design tool that leverages the MATLAB and Simulink environment to define, test and implement production quality DSP algorithms in programmable logic in a fraction of traditional RTL development times.

The tool provides:

• 100+ optimized DSP blocks, many with C simulation models for 2-3X faster simulation vs RTL
• Integration of RTL, IP, Simulink, MATLAB and C/C++ components of a DSP system
• Bit and cycle accurate floating and fixed-point simulations
• Hardware co-simulation to accelerate simulation and validate algorithm on working hardware
• Automatic code generation from Simulink to packaged IP or low-level HDL
• Automatic generation of HDL test bench, including test vectors

Learn more about Vivado System Generator for DSP:

• Introduction to Vitis Model Composer (Video)
• Vitis Model Composer (Documentation)

High Level Synthesis

High-Level Synthesis, include Vitis unified software platform, enables portable C, C++ and System C algorithm specifications to be directly targeted into AMD FPGA & Adaptive SoCs without the need to create RTL. Just as there are compilers from C/C++ to different processor architectures, the HLS compiler provides the same functionality from C/C++ to AMD FPGA & Adaptive SoCs.

Learn more about Vivado High Level Synthesis:

• Getting Started with Vitis High-Level Synthesis (Video)
• Vitis High Level Synthesis User Guide (Documentation)