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Arria® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

1. Device Information

2. Interface Protocols

3. Design Planning

4. Design Entry

5. Simulation and Verification

6. Implementation and Optimization

7. Timing Analysis

8. On-Chip Debug

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1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Arria® 10 Core Fabric and General Purpose I/Os Handbook
Arria® 10 Device Datasheet
Arria® 10 Device Overview
Arria® 10 GX/GT Device Errata and Design Recommendations
Arria® 10 Transceiver PHY User Guide
Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, and Stratix® 10 Devices
FPGA I/O Phase-Locked Loop (FPGA IOPLL) IP Core User Guide
FPGA Chip ID IP Cores User Guide
Arria® 10 External Memory Interfaces IP User Guide
Arria® 10 External Memory Interfaces IP Design Example User Guide
Arria® 10 External Memory Interface IP Core Release Notes
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
FPGA Voltage Sensor IP Core User Guide
Early Power Estimator for Arria® 10 FPGAs User Guide
FPGA Temperature Sensor IP Core User Guide
Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
FPGA Parallel Flash Loader IP Core User Guide
FPGA ASMI Parallel II IP Core User Guide
FPGA ASMI Parallel IP Core User Guide
FPGA Remote Update IP Core User Guide
PHYLite Design Implementation Guidelines
AN 556: Using the Design Security Features in FPGAs
AN 496: Using the Internal Oscillator IP Core
AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families
AN 756: FPGA GPIO to FPGA
AN 711: Power Reduction Features in Arria® 10 Devices
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria® 10 Devices
AN 737: SEU Detection and Recovery in Arria® 10 Devices
AN 738: Arria® 10 Device Design Guidelines
AN 742: PMBus SmartVID Controller Reference Designs
AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software

2. Interface Protocols

Documentation

User Guides / Application Notes
Ethernet
FPGA Triple-Speed Ethernet IP Core User Guide
FPGA Low Latency Ethernet 10G MAC User Guide
Arria® 10 25 Gbps Ethernet IP Core User Guide
50 Gbps Ethernet IP Core User Guide
Low Latency 100-Gbps Ethernet IP Core User Guide
Low Latency 40-Gbps Ethernet IP Core User Guide
Arria® 10 Transceiver PHY User Guide
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
AN 735: FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines
AN 808: Migration Guidelines from Arria® 10 to Stratix® 10 for 10G Ethernet Subsystem
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria® 10 Devices
AN 699: Using the FPGA Ethernet Design Toolkit
AN 701: Scalable Low Latency Ethernet 10G MAC Using Arria® 10 1G/10G PHY
AN 794: Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
AN 744: Scalable Triple Speed Ethernet Reference Design for Arria® 10 Devices
User Guides
Audio and Video
FPGA SDI II IP Core User Guide

4. Design Entry

Documentation

If you are new to these languages, you can use online examples or built-in VHDL or Verilog templates to get you started which are discussed in theQuartus® Prime Pro Edition Used Guide: Design Recommendations

The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these template, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Edition Handbook.

The Quartus® Prime design software also comes with High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for FPGA products.

5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Standard Edition User Guide: Third-party Simulation
Quartus® Prime Pro Edition User Guide: Third-party Simulation
Simulation Quick-Start for ModelSim*-Altera® FPGA Edition
Avalon® Verification IP Suite User Guide
FPGA Software Installation and Licensing
Simulating the a8251 Model with the Visual IP Software
Simulating the a8259 Model with the Visual IP Software
Simulating the Reed-Solomon Model with the Visual IP Software
Simulating the Turbo Encoder/Decoder Model with the Visual IP Software
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix® 10 Devices
AN 720: Simulating the ASMI Block in Your Design
AN 351: Simulating Nios® II Processor Designs
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
Simulating FPGA Devices with IBIS Models
Software Downloads
Quartus® Prime Software

6. Implementation and Optimization

Documentation

7. Timing Analysis

Documentation

8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Programmer User Guide: Quartus® Prime Pro Edition
Analyzing and Debugging Designs with System Console
Debug Tools User Guide: Quartus® Prime Pro Edition
FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide
FPGA-Adaptive Software Debug and Performance Analysis
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug
ByteBlaster II Download Cable User Guide
FPGA USB Download Cable User Guide
FPGA Download Cable II User Guide
EthernetBlaster Communications Cable User Guide
BSDL Support
AN 827: Unified Tool for Generating Programming Files
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer
AN 799: Quick Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile
AN 693: Remote Hardware Debugging over TCP/IP for FPGA SoC
AN 541: SerialLite II Hardware Debugging Guide
AN 543: Debugging Nios® II Software Using the Lauterbach Debugger
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 624: Debugging with System Console over TCP/IP

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

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Board Developer Center

Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.

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Embedded Software Developer Center

Contains guidance on how to design in an embedded environment with SoC FPGAs.

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FPGA Developer Center

Contains resources to complete your Altera® FPGA design.