Zen+ is the name for acomputer processormicroarchitecture byAMD. It is the successor to the first genZen microarchitecture,^[3] and was first released in April 2018,^[4] powering the second generation of Ryzen processors, known asRyzen 2000 for mainstream desktop systems, Threadripper 2000 for high-end desktop setups and Ryzen 3000G (instead of 2000G) foraccelerated processing units (APUs).

Zen+ usesGlobalFoundries'12 nm fabrication process,^[5] an optimization of the 14 nm process used for Zen, with only minor design rule changes.^[6] This means that the die sizes between Zen and Zen+ are identical as AMD chose to use the new smaller transistors to increase the amount of empty space, or "dark silicon", between the various features on the die. This was done to improve power efficiency & reduce thermal density to allow for higherclock speeds, rather than design an entirely newfloorplan for a physically smaller die (which would have been significantly more work and thus more expensive).^[7] These process optimizations allowed 12 nm Zen+ to clock about +250 MHz (≈6%) higher, or to lower power consumption when at the same frequency by 10%, when compared to their prior 14 nm Zen products.^[8] Although conversely at themicroarchitecture level, Zen+ had only minor revisions versus Zen.^[6] Known changes to the microarchitecture include improved clock speed regulation in response to workload ("Precision Boost 2"),^[9] reduced cache and memory latencies (some significantly so), increased cache bandwidth, and finally improvedIMC performance allowing for betterDDR4 memory support (officiallyJEDEC rated to support up to 2933 MHz compared to just 2666 MHz on the prior Zen core),^[10] and fixed many hardware bugs found on Zen 1, such asfTPM /PSP bugs on Zen 1, andSVM /SLAT bugs on Zen 1.

Zen+ also supports improvements in the per-core clocking features, based on core utilization and CPU temperatures.^[6] These changes to the core utilization, temperature, and power algorithms are branded as "Precision Boost 2" and "XFR2" ("eXtended Frequency Range 2"), evolutions of the first-generation technologies in Zen. On Zen, XFR gave an additional 50 to 200 MHz clock speed increase (in 25 MHz increments) over the maximum Precision Boost clocks. For Zen+, XFR2 is no longer listed as a separate clock modifier. Instead, the XFR temperature, power, and clock monitoring and logic feeds into the Precision Boost 2 algorithm to adjust clocks and power consumption opportunistically and dynamically.^[11][12]

Ultimately, the changes in Zen+ resulted in a 3% improvement inIPC over Zen; which in conjunction with 6% higher clock speeds resulted in up to 10% overall increase in performance.^[6]

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APU features table

Common features of Ryzen 2000 desktop CPUs:

• Socket:AM4.
• All the CPUs supportDDR4-2933 indual-channel mode, except for R7 2700E, R5 2600E, R5 1600AF and R3 1200AF which support it at DDR4-2666 speeds.
• All the CPUs support 24PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• L1cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• Fabrication process:GlobalFoundries12LP (14LP+).

Common features of Ryzen 2000 HEDT CPUs:

• Socket:TR4.
• All the CPUs supportDDR4-2933 inquad-channel mode.
• All the CPUs support 64PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• L1cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• Fabrication process:GlobalFoundries12LP (14LP+).

Common features ofZen+ based desktop APUs:

• Socket:AM4.
• All the CPUs supportDDR4-2933 indual-channel mode, whileAthlon Pro 300GE andAthlon Silver Pro 3125GE support only DDR4-2666.
• L1cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16PCIe 3.0 lanes.
• Includes integratedGCN 5th generation GPU.
• Fabrication process:GlobalFoundries12LP.

Common features of Ryzen 3000 notebook APUs:

• Socket: FP5.
• All the CPUs supportDDR4-2400 indual-channel mode.
• L1cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16PCIe 3.0 lanes.
• Includes integratedGCN 5th generation GPU.
• Fabrication process:GlobalFoundries12LP (14LP+).

In 2022, AMD announced the R2000 series of embedded APUs.^[44]

Wikimedia Commons has media related toZen microarchitecture.

• AMD K9
• AMD K10
• Jim Keller (engineer)
• Ryzen
• Steamroller (microarchitecture)
• Zen (microarchitecture)
• Zen 2

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