Inparallelcomputer architectures, asystolic array is a homogeneousnetwork of tightly coupleddata processing units (DPUs) called cells ornodes. Each node or DPU independently computes a partial result as a function of the data received from its upstream neighbours, stores the result within itself and passes it downstream. Systolic arrays were first used inColossus, which was an early computer used to break GermanLorenz ciphers duringWorld War II.^[1] Due to the classified nature of Colossus, they were independently invented or rediscovered byH. T. Kung andCharles Leiserson who described arrays for many dense linear algebra computations (matrix product, solving systems oflinear equations,LU decomposition, etc.) for banded matrices. Early applications include computinggreatest common divisors of integers and polynomials.^[2] They are sometimes classified asmultiple-instruction single-data (MISD) architectures underFlynn's taxonomy, but this classification is questionable because a strong argument can be made to distinguish systolic arrays from any of Flynn's four categories:SISD,SIMD,MISD,MIMD, as discussed later in this article.

The parallel inputdata flows through a network of hard-wiredprocessor nodes, which combine, process,merge orsort the input data into a derived result. Because thewave-like propagation of data through a systolic array resembles thepulse of the human circulatory system, the namesystolic was coined from medical terminology. The name is derived fromsystole as an analogy to the regular pumping of blood by the heart.

Systolic arrays are often hard-wired for specific operations, such as "multiply and accumulate", to perform massivelyparallel integration,convolution,correlation,matrix multiplication or data sorting tasks. They are also used fordynamic programming algorithms, used in DNA and proteinsequence analysis.

A systolic array typically consists of a largemonolithicnetwork of primitive computingnodes which can be hardwired or software configured for a specific application. The nodes are usually fixed and identical, while the interconnect is programmable. The more generalwavefront processors, by contrast, employ sophisticated and individually programmable nodes which may or may not be monolithic, depending on the array size and design parameters. The other distinction is that systolic arrays rely onsynchronous data transfers, whilewavefront tend to workasynchronously.

Unlike the more commonVon Neumann architecture, where program execution follows a script of instructions stored in common memory,addressed and sequenced under the control of theCPU'sprogram counter (PC), the individual nodes within a systolic array are triggered by the arrival of new data and always process the data in exactly the same way. The actual processing within each node may be hard wired or blockmicro coded, in which case the common node personality can be block programmable.

The systolic array paradigm with data-streams driven by datacounters, is the counterpart of the Von Neumann architecture with instruction-stream driven by a program counter. Because a systolic array usually sends and receives multiple data streams, and multiple data counters are needed to generate these data streams, it supportsdata parallelism.

A major benefit of systolic arrays is that all operand data and partial results are stored within (passing through) the processor array. There is no need to access external buses, main memory or internal caches during each operation as is the case with Von Neumann orHarvard sequential machines. The sequential limits onparallel performance dictated byAmdahl's Law also do not apply in the same way, because data dependencies are implicitly handled by the programmablenode interconnect and there are no sequential steps in managing the highly parallel data flow.

Systolic arrays are therefore extremely good at artificial intelligence, image processing, pattern recognition, computer vision and other tasks that animal brains do particularly well. Wavefront processors in general can also be very good at machine learning by implementing self configuring neural nets in hardware.

While systolic arrays are officially classified asMISD, their classification is somewhat problematic. Because the input is typically a vectorof independent values, the systolic array is definitely notSISD. Since theseinput values are merged and combined into the result(s) and do not maintain theirindependence as they would in aSIMD vector processing unit, thearray cannot be classified as such. Consequently, the array cannot be classified as aMIMD either, because MIMD can be viewed as a mere collection of smaller SISD andSIMD machines.

Finally, because the dataswarm is transformed as it passes through the array fromnode to node, the multiple nodes are not operating on the same data, which makes the MISD classification amisnomer. The other reason why a systolic array should not qualify as aMISD is the same as the one which disqualifies it from the SISD category: The input data is typically a vector not asingledata value, although one could argue that any given input vector is a single item of data.

In spite of all of the above, systolic arrays are often offered as a classic example of MISD architecture in textbooks onparallel computing and in engineering classes. If the array is viewed from the outside asatomic it should perhaps be classified asSFMuDMeR = single function, multiple data, merged result(s).

Systolic arrays use a pre-defined computational flow graph that connects their nodes.Kahn process networks use a similar flow graph, but are distinguished by the nodes working in lock-step in the systolic array: in a Kahn network, there are FIFO queuesbetween each node.

A systolic array is composed of matrix-like rows ofdata processing units called cells. Data processing units (DPUs) are similar tocentral processing units (CPUs), (except for the usual lack of aprogram counter,^[3] since operation istransport-triggered, i.e., by the arrival of a data object). Each cell shares the information with its neighbors immediately after processing. The systolic array is often rectangular where data flows across the array between neighbourDPUs, often with different data flowing in different directions. The data streams entering and leaving the ports of the array are generated by auto-sequencing memory units, ASMs. Each ASM includes a datacounter. Inembedded systems a data stream may also be input from and/or output to an external source.

An example of a systolicalgorithm might be designed formatrix multiplication. Onematrix is fed in a row at a time from the top of the array and is passed down the array, the other matrix is fed in a column at a time from the left hand side of the array and passes from left to right. Dummy values are then passed in until each processor has seen one whole row and one whole column. At this point, the result of the multiplication is stored in the array and can now be output a row or a column at a time, flowing down or across the array.^[4]

Systolic arrays are arrays ofDPUs which are connected to a small number of nearest neighbour DPUs in a mesh-like topology. DPUs perform a sequence of operations on data that flows between them. Because the traditional systolic array synthesis methods have been practiced by algebraic algorithms, only uniform arrays with only linear pipes can be obtained, so that the architectures are the same in all DPUs. The consequence is, that only applications with regular data dependencies can be implemented on classical systolic arrays. LikeSIMD machines, clocked systolic arrays compute in "lock-step" with each processor undertaking alternate compute | communicate phases. But systolic arrays with asynchronous handshake between DPUs are calledwavefront arrays.One well-known systolic array is Carnegie Mellon University'siWarp processor, which has been manufactured by Intel. An iWarp system has a linear array processor connected by data buses going in both directions.

Systolic arrays (also known aswavefront processors), were first described byH. T. Kung andCharles E. Leiserson, who published the first paper describing systolic arrays in 1979. However, the first machine known to have used a similar technique was theColossus Mark II in 1944.

Horner's rule for evaluating a polynomial is:

${\displaystyle y=(\dots (((a_n\cdot x+a_{n-1})\cdot x+a_{n-2})\cdot x+a_{n-3})\cdot x+\dots +a_1)\cdot x+a_0.}$

A linear systolic array in which the processors are arranged in pairs: one multiplies its input by${\displaystyle x}$ and passes the result to the right, the next adds${\displaystyle a_j}$ and passes the result to the right.

Consider a chain of processing elements (PEs), each performing amultiply-accumulate operation. It processes input data (${\displaystyle x_i}$) and weights (${\displaystyle w_i}$) systolically, meaning data flows through the array in a regular, rhythmic manner. The weights remain stationary within each PE, while the input data and partial sums (${\displaystyle y_i}$) move in opposite directions.

Each PE performs the following operation:where:

• ${\displaystyle x_{in}}$ is the input data.
• ${\displaystyle y_{in}}$ is the incoming partial sum.
• ${\displaystyle w}$ is the weight stored in the PE.
• ${\displaystyle x_{out}}$ is the output data (passed to the next PE).
• ${\displaystyle y_{out}}$ is the updated partial sum.

From the left, the input stream is${\displaystyle \dots ,x_3,0,x_2,0,x_1}$, and from the right, the output stream is${\displaystyle y_1,y_2,y_3,\dots }$. If${\displaystyle y_1,x_1}$ enter the rightmost PE simultaneously, then the leftmost PE outputsThis is the 1-dimensional convolution. Similarly, n-dimensional convolution can be computed by an n-dimensional array of PEs.

Many other implementations of the 1D convolutions are available, with different data flows.^[5]

See^[5] Figure 12 for an algorithm that performs on-the-flyleast-squares using one- and two-dimensional systolic arrays.

• Cisco PXF network processor is internally organized as systolic array.^[6]
• Google’sTPU is also designed around a systolic array.
• Paracel FDF4T TestFinder text search system^[7]
• Paracel FDF4G GeneMatcher Biological (DNA and Protein) search system
• Inferentia chip atAmazon Web Services^[8]
• MIT Eyeriss is a systolic array accelerator for convolutional neural networks.^[9][10]

• MISD – multiple instruction single data, example: systolic arrays
• iWarp – systolic array computer, VLSI, Intel/CMU
• WARP (systolic array) – systolic array computer, GE/CMU
• Tensor Processing Unit –AI acceleratorASIC

This article includes a list ofgeneral references, butit lacks sufficient correspondinginline citations. Please help toimprove this article byintroducing more precise citations.(April 2011) (Learn how and when to remove this message)

• H. T. Kung, C. E. Leiserson: Algorithms for VLSI processor arrays; in: C. Mead, L. Conway (eds.): Introduction to VLSI Systems; Addison-Wesley, 1979
• S. Y. Kung: VLSI Array Processors; Prentice-Hall, Inc., 1988
• N. Petkov: Systolic Parallel Processing; North Holland Publishing Co, 1992

• Instruction Systolic Array (ISA)
• 'A VLSI Architecture for Image Registration in Real Time' (Based on systolic array), Vol. 15, September 2007

• Parallel computing
• Reconfigurable computing

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