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Serial general-purpose input/output (SGPIO) is a four-signal (or four-wire) bus used between ahost bus adapter (HBA) and abackplane. Of the four signals, three are driven by the HBA and one by the backplane. Typically, the HBA is a storage controller located inside a server, desktop, rack or workstation computer that interfaces withhard disk drives orsolid-state drives to store and retrieve data. It is considered an extension of thegeneral-purpose input/output (GPIO) concept.–The SGPIO specification is maintained by theSmall Form Factor Committee in theSFF-8485 standard. TheInternational Blinking Pattern Interpretation indicates how SGPIO signals are interpreted into blinkinglight-emitting diodes (LEDs) ondisk arrays and storage back-planes.
SGPIO was developed as an engineering collaboration between American Megatrends Inc, at the time makers of back-planes, and LSI-Logic in 2004. SGPIO was later published by the SFF committee as specificationSFF-8485.
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The SGPIO signal consists of 4 electrical signals; it typically originates from ahost bus adapter (HBA). iPass connectors (Usually SFF-8087 or SFF-8484) carry both SAS/SATA electrical connections between the HBA and the hard drives as well as the 4 SGPIO signals.
Abackplane is a circuit board with connectors and power circuitry into which hard drives are attached; they can have multiple slots, each of which can be populated with a hard drive. Typically the back-plane is equipped withLEDs which by their color and activity, indicate the slot's status; typically, a slot's LED will emit a particular color or blink pattern to indicate its current status.
Although many hardware vendors define their own proprietary LED blinking pattern, the common standard for SGPIO interpretation and LED blinking pattern can be found in theIBPI specification.
On back-planes, vendors use typically 2 or 3 LEDs per slot – in both implementations a green LED indicates presence and/or activity – for back-planes with 2 LEDs per slot, the second LED indicatesStatus whereas in back-planes with 3 LEDs the second and third indicateLocate andFail.
The SGPIO bus consists of 4 signal lines and originates at the HBA, referred to as theinitiator and ends at aback-plane, referred to as thetarget. If a back-plane (ortarget) is not present the HBA may still drive the bus without any harm to the system; if one does exist, it can communicate back to the HBA using the 4th wire.
The SGPIO bus is anopen collector bus with 2.0 kΩ pull-up resistors located at the HBA and the back-plane – as on any open collector bus information is transferred by devices on the bus pulling the lines toground (GND) using an open collector transistor or open drainFET.
The SGPIO bus has a dedicated clock line driven by the initiator (its maximum clock rate is 100 kHz), although many implementations use slower ones (typically 48 kHz).
This line is synchronous to the clock and is used to indicate the start of a new frame of data; a new SGPIO frame is indicated by SLoad being high at a rising edge of a clock after having been low for at least 5 clock cycles. The following 4 falling clock edges after a start condition is used to carry a4-bit value from the HBA to the back-plane; the definition of this value is proprietary and varies between system vendors.
This line carries 3 bits of data from the HBA to the backplane: the first bit typically carriesactivity; the second bit carrieslocate; and the third bit carriesfail. A low value for the first bit indicatesno activity and a high value indicatesactivity.
This line is used by the back-plane and indicates some condition on the back-plane back to the HBA. The first bit being high commonly indicates the presence of a drive. The two following bits are typically unused, and driven low. Because this line would be high for all 3 bits when no backplane is connected, an HBA can detect the presence of a back-plane by the second or third bit of the SDataIn being driven low.
The SDataIn and SdataOut then repeats with 3 clocks per drive until the last drive is reached, and the cycle starts over again.
There are varieties in how the SGPIO bus is implemented between vendors of HBAs and storage controllers - some vendors will send a continuous stream of data which is advantageous to quickly update the LEDs on a backplane after cables are removed and re-inserted, while others send data only when there is a need to update the LED pattern.
SGPIO and the SGPIO spec. is generally adopted and implemented in products from most major HBA and storage controller vendors such asLSI,Intel,Adaptec,Nvidia,Broadcom,Marvell Technology Group andPMC-Sierra. Most products shipping with support forSAS andSATA drives support this standard.
The SGPIO spec calls for the target to turn off all indicators when SClock, SLoad and SDataOut have been high for 64 ms; in practice this is not consistently followed by all vendors. Also, in some vendors' implementations the clock may be halted sporadically or stopped during or between cycles. Another – rather impractical – variation between vendors is the state in which the clock is left after a cycle.
The idea behind this specification was to be able to use low costCPLDs ormicrocontrollers on a back-plane to drive LEDs; in practice, it has been found that there are variations in timing and interpretations of the bits between vendors, thus a simple CPLD would only work for a specific implementation thoroughly tested with one product from one vendor.[citation needed] A microcontroller is more applicable for this purpose, although the 4-bit SGPIO interface custom bus is not implemented on them[citation needed] – sampling of the 4-bit lines usingGPIOs 100 kHz bit operations is too slow[clarification needed] for many low-cost microcontrollers to handle whilst handling LED and other functions simultaneously. The length of the bit stream varies between HBA or storage controller; some vendors will stop the bit-stream when reaching the desired drive, while others will clock it all the way through. Some SAS-expander's bit streams may be as long as 108 (36×3) bits.
The safest implementation which ensures compatibility between all HBA and storage controller vendors is to use anASIC, specifically, a combination of a microcontroller core with a hardware SGPIO interface; this concept was patented[citation needed] in 2006 byAMI and implemented in a series of backplane controller chips named theMG9071,MG9072,MG9077, andMG9082.
These chips will receive 1 or 2 SGPIO streams and drive LEDs accordingly; the latest chip from AMI, theMG9077, can be configured by pull-up and pull-down resistors to adopt to 16 different configurations of SGPIO buses and drive the LEDs accordingly. Since the availability of these chips from AMI, majorOEMs includingNEC,Hitachi,Supermicro,IBM,Sun Microsystems, and others are using them on their back-planes to receive the SGPIO streams from a variety of HBA vendors and on-board controller chips to consistently drive LEDs with a pre-determined blinking pattern.