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Programmed input–output (alsoprogrammable input/output,programmed input/output,programmed I/O,PIO) is a method ofdata transmission, viainput/output (I/O), between acentral processing unit (CPU) and aperipheral device,[1] such as aParallel ATA storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, indirect memory access (DMA) operations, the CPU is uninvolved in the data transfer.
The term can refer to eithermemory-mapped I/O (MMIO) or port-mapped I/O (PMIO). PMIO refers to transfers using a specialaddress space outside of normal memory, usually accessed with dedicated instructions, such asIN andOUT inx86 architectures. MMIO[2] refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.
The best known example of a PC device that uses programmed I/O is the Parallel AT Attachment (PATA) interface; however, the AT Attachment interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, keyboard and mousePS/2 ports, legacyMIDI andjoystick ports, the interval timer, and older network interfaces.
The PIO interface is grouped into different modes that correspond to differenttransfer rates. Theelectrical signaling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually Ultra Direct Memory Access (UDMA)) interface was created to increase performance. The simple digital logic needed to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are unneeded as inembedded systems, or withfield-programmable gate array (FPGA) chips, where PIO mode can be used with no significant performance loss.
Two additional advanced timing modes have been defined in theCompactFlash specification 2.0. Those are PIO modes 5 and 6. They are specific to CompactFlash.
| Mode | Maximum transfer rate (MB/s) | Minimum cycle time | Standard where spec is defined |
|---|---|---|---|
| Mode 0 | 3.3 | 600ns | ATA-1 |
| Mode 1 | 5.2 | 383ns | ATA-1 |
| Mode 2 | 8.3 | 240ns | ATA-1 |
| Mode 3 | 11.1 | 180ns | ATA-2 |
| Mode 4 | 16.7 | 120ns | ATA-2 |
| Mode 5 | 20 | 100ns | CompactFlash 2.0 |
| Mode 6 | 25 | 80ns | CompactFlash 2.0 |
A PIO Mode 5 was proposed[3] with operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and theDMA standard ultimately obviated it. While nohard disk drive was ever manufactured to support this mode, somemotherboard manufacturers preemptively providedBIOS support for it. PIO Mode 5 can be used with CompactFlash cards connected to ATA via CF-to-ATA adapters.