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ThePowerPC 600 family was the first family ofPowerPCprocessors built. They were designed at the Somerset facility inAustin, Texas, jointly funded and staffed by engineers fromIBM andMotorola as a part of theAIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors forpersonal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

ThePowerPC 601 was the first generation of microprocessors to support the basic32-bitPowerPCinstruction set. The design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992. The first 601 processors were introduced in an IBMRS/6000workstation in October 1993 (alongside its more powerful multichip cousinIBMPOWER2 line of processors) and the first ApplePower Macintoshes on March 14, 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an extremely aggressive schedule while including substantially new functionality (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's firstsymmetric multiprocessing (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBMRISC Single Chip (RSC) processor,^[1] but also included support for the vast majority of the new PowerPC instructions not in thePOWER instruction set. While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unifiedI/Obus structure and SMP/memory coherency support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning. Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM and software developers in their transitions to PowerPC. From start of design totape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.

In order to help the effort to rapidly incorporate the88110 bus architecture to the 601 for the benefit of the alliance and its customers, Motorola management provided not only the 88110 bus architecture specifications, but also a handful of 88110 bus-literate designers to help with the 60x bus logic implementation and verification. Given the Apple system design team was familiar with the I/O bus structure from Motorola's 88110 and this I/O bus implementation was well defined and documented, the 601 team adopted the bus technology to improve time to market. The bus was renamed the60x bus once implemented on the 601.^[2] These Motorola (and a small number of Apple) designers joined over 120 IBM designers in creating the 601.

Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their supportASICs and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses hadn't been adopted).Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.

This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604,G3,G4 and Motorola/FreescalePowerQUICC processors.

The chip was designed to suit a wide variety of applications and had support for externalL2 cache andsymmetric multiprocessing. It had four functional units, including afloating-point unit, aninteger unit, a branch unit and a sequencer unit. The processor also included amemory management unit. The integerpipeline was four stages long, the branch pipeline two stages long, the memory pipeline five stages long, and the floating-point pipeline six stages long.

First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and by Motorola as the MPC601. It operated at speeds ranging from 50 to 80 MHz. It was fabricated using a 0.6 μmCMOS process with four levels ofaluminum interconnect. The die was 121 mm² large and contained 2.8 million transistors. The 601 has a 32 KB unifiedL1 cache, a capacity that was considered large at the time for an on-chip cache. Thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competingIntelPentium. The PowerPC 601 was used in the firstPower Macintosh computers fromApple, and in a variety ofRS/6000 workstations and SMP servers from IBM andGroupe Bull.

IBM was the sole manufacturer of the 601 and 601+ microprocessors in itsBurlington, Vermont andEast Fishkill, New York production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola. These facts are somewhat obscured given there are various pictures of the "Motorola MPC601", particularly one specific case of masterful Motorola marketing where the 601 was named one ofTime Magazine's 1994 "Products of the Year" with a Motorola marking.

• PowerPC 601 Microprocessor, lecture by Keith Diefendorff

An updated version, thePowerPC 601v orPowerPC 601+, operating at 90 to 120 MHz was introduced in 1994. It was fabricated in a newer 0.5 μm CMOS process with four levels of interconnect, resulting in a die measuring 74 mm². The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBMEDA tools on IBM systems and were fabricated in IBM-only facilities.^[3][4][5][6]

ThePowerPC 603 was the first processor implementing the complete 32-bitPowerPC Architecture as specified. Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2 W and a small die of 85 mm².^{[7][8][9][10]} It was designed to be a low cost, low power processor for portable applications. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating-point unit,branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120 MHz at 3.8 V.^[10] The 603 core did not have hardware support forSMP.

The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm² large drawing 2.2 W at 80 MHz.^[10][11] The 603 architecture is the direct ancestor to thePowerPC 750 architecture, marketed by Apple as the PowerPC "G3".

The 603 was intended to be used for portableApple Macintosh computers but could not run68K emulation software with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line.^[12][13] This caused the delay of the ApplePowerBook 5300 andPowerBook Duo 2300, as Apple chose to wait for a processor revision. Apple's use of the 603 in thePerforma 5200 line led to the processor getting a poor reputation. Aside from the issue of 68K emulation performance, the Performa machines shipped with a variety of design flaws, some of them severe, related to other aspects of the computers' design, including networking performance and stability, bus problems (width, speed, contention, and complexity), ROM bugs, and hard disk performance.^[14][15] None of the problems of the 5200 line, aside from 68K emulation performance, were inherently due to the 603. Rather, the processor was retrofitted to be used with 68K motherboards and other obsolete parts.^[16] The site Low End Mac rates the Performa 5200 as the worst Mac of all-time.^[17] The 603 found widespread use in different embedded appliances.^{[citation needed]}

The performance issues of the 603 were addressed in thePowerPC 603e. The L1 cache was enlarged and enhanced to 16 KB four-way set-associative data and instruction caches. The clock speed of the processors was doubled too, reaching 200 MHz. Shrinking the fabrication process to 350 nm allowed for speeds of up to 300 MHz. This part is sometimes calledPowerPC 603ev. The 603e and 603ev have 2.6 million transistors each and are 98 mm² and 78 mm² large respectively. The 603ev draws a maximum of 6 W at 300 MHz.^[18][19]

The PowerPC 603e was the first mainstream desktop processor to reach 300 MHz, as used in thePower Macintosh 6500. The 603e was also used in accelerator cards fromPhase5 for theAmiga line of computers, with CPUs ranging in speeds from 160 to 240 MHz. The PowerPC 603e is still sold today by IBM and Freescale, and others likeAtmel andHoneywell who makes theradiation hardened variantRHPPC. The PowerPC 603e was also the heart of theBeBox fromBe Inc. The BeBox is notable since it is amultiprocessing system, something the 603 wasn't designed for. IBM also used PowerPC 603e processors in theIBM ThinkPad 800 series. In certain digital oscilloscope series,LeCroy used the PowerPC 603e as the main processor.^[20][21] The 603e processors also power all 66satellites in theIridium satellite phone fleet. The satellites each contain seven Motorola/Freescale PowerPC 603e processors running at roughly 200 MHz each. A custom 603e processor is also used in theMark 54 Lightweight Torpedo.

The PowerPC 603e core, renamedG2 byFreescale, is the basis for many embeddedPowerQUICC II processors, and, as such, it keeps on being developed. Freescale's PowerQUICC IISoC processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz. The G2 name is also used as a retronym for the 603e and 604 processors to align with the G3, G4, and the G5.

Freescale has enhanced the 603e core, calling ite300, in thePowerQUICC II Pro embedded processors. Larger 32/32 KB L1 caches and other performance enhancing measures were added. Freescale's PowerQUICC II ProSoC processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz. The e300 is also the core of theMPC5200B SoC processor that is used in the smallEFIKA computer.

ThePowerPC 604 was introduced in December 1994 alongside the 603 and was designed as a high-performance chip forworkstations and entry-level servers and as such had support forsymmetric multiprocessing in hardware. The 604 was used extensively inApple's high-end systems and was also used inMacintosh clones, IBM's low-endRS/6000 servers and workstations,Amiga accelerator boards, and as an embedded CPU for telecom applications.

The 604 is asuperscalar processor capable of issuing four instructions simultaneously. The 604 has a six-stage pipeline and six execution units that can work in parallel, finishing up to six instructions every cycle. Two simple and one complexinteger units, onefloating-point unit, one branch-processing unit managingout-of-order execution and one load/store unit. It has separate 16 KB data and instruction L1 caches. The external interface is a 32- or 64-bit 60x bus that operates at clock rates up to 50 MHz.

The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5 μm CMOS process with four levels of interconnect. The die measured 12.4 mm by 15.8 mm (196 mm²) and drew 14-17 W at 133 MHz. It operated at speeds between 100 and 180 MHz.^[22][23][24]

• Power PC 604 RISC microprocessor, lecture by Marvin Denman

ThePowerPC 604e was introduced in July 1996 and added a condition register unit and separate 32 KB data and instruction L1 caches among other changes to its memory subsystem and branch prediction unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35 μm CMOS process with five levels of interconnect. The die was 148 mm² or 96 mm² large, manufactured by Motorola and IBM respectively, drawing 16–18 W at 233 MHz. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.^[25][26]

ThePowerPC 604ev,604r or"Mach 5" was introduced in August 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption. The die was 47 mm² small manufactured on a 0.25 μm CMOS process with five levels of interconnect, and drew 6 W at 250 MHz. It operated at speeds between 250 and 400 MHz and supported a memory bus up to 100 MHz.

While Apple dropped the 604ev in 1998 in favor for thePowerPC 750, IBM kept using it in entry-level models of itsRS/6000 computers for several years.

ThePowerPC 620 was the first implementation of the entire64-bit PowerPC architecture. It was a second generation PowerPC alongside the 603 and 604, but geared towards the high-end workstation and server market. It was powerful on paper and was initially supposed to be launched alongside its brethren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e surpassed it.^[27] The 620 was therefore never produced in large quantities and found very little use. The sole user of PowerPC 620 wasGroupe Bull in its EscalaUNIX machines, but they didn't deliver any large numbers. IBM, which intended to use it in workstations and servers, decided to wait for the even more powerfulRS64 andPOWER3 64-bit processors instead.

The 620 was produced by Motorola in a 0.5 μm process. It had 6.9 million transistors and the die had an area of 311 mm². It operated at clock rates between 120 and 150 MHz, and drew 30 W at 133 MHz. A later model was built using a 0.35 μm process, enabling it to reach 200 MHz.^{[further explanation needed]}

The 620 was similar to the 604. It has a five-stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units. With larger 32 KB instruction and data caches, support for a L2 cache that may have a capacity of 128 MB, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604. The floating-point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instructions in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.^{[further explanation needed]}

The system bus was a wider and faster 128-bit memory bus called the6XX bus. It was designed to be a system bus for multiprocessor systems where processors, caches, memory and I/O was to be connected, assisted by a system control chip. It supports both 32- and 64-bit PowerPC processors, memory addresses larger than 32 bits, andNUMA environments. It was also used in POWER3, RS64 and 601, as well as 604-based RS/6000 systems (with a bridge chip).^[28] The bus later evolved into theGX bus of thePOWER4, and laterGX+ andGX++ inPOWER5 andPOWER6 respectively. The GX bus is also used in IBM'sz10 andz196System z mainframes.

• Contribution to the history of Unix at Bull (Interesting reading concerning the use of PowerPC 620 at Bull. In French)

ThePowerPC 602 was a stripped-down version of PowerPC 603, specially made for game consoles by Motorola and IBM, introduced in February 1995.^[29] It has smaller L1 caches (4 KB instruction and 4 KB data), a single-precision floating-point unit^[29] and a scaled back branch prediction unit. It was offered at speeds ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It consisted of 1 million transistors and it was 50 mm² large manufactured in a 0.5 μm, CMOS process with four levels of interconnect.^[30]

3DO developed theM2 game console that used two PowerPC 602,^[29][31] but it was never marketed.

• Article at the CPUShack

On October 21, 1996, thefabless semiconductor companyQuantum Effect Devices (QED) announced a PowerPC 603-compatible processor named "PowerPC 603q" at theMicroprocessor Forum. Despite its name, it did not have anything in common with any other 603. It was a from the ground up implementation of the 32-bit PowerPC architecture targeted at the high-end embedded market developed over two years. As such, it was small, simple, energy efficient, but powerful; equaling the more expensive 603e while drawing less power. It had an in-order, five-stage pipeline with a single integer unit, adouble-precision floating-point unit (FPU) and separate 16 KB instruction and 8 KB data caches. While the integer unit was a brand new design, the FPU was derived from theR4600 to save time. It was 69 mm² small using a 0.5 μm fabrication process and drew just 1.2 W at 120 MHz.^[32][33]

The 603q was designed for Motorola, but they withdrew from the contract before the 603q went into full production. As a result, the 603q was canceled as QED could not continue to market the processor since they lacked a PowerPC license of their own.

"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC.^[34][35][36] It supposedly was renamed "PowerPC 750" in response toExponential Technology'sx704 processor that was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

Similar to PowerPC 613, the"PowerPC 614" might have been a name given by Motorola to a third generation PowerPC,^[34][36] and later renamed by the same reason as 613. It's been suggested that the part was renamed "PowerPC 7400", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

The "PowerPC 615" is a PowerPC processor announced by IBM in 1994, but which never reachedmass production. Its main feature was to incorporate anx86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions.^[37] An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 wereMinix and a special development version ofOS/2.^[38]

It was 330 mm² large and manufactured by IBM on a 0.35 μm process. It was pin compatible withIntel'sPentium processors and comparable in speed. The processor was introduced only as a prototype and the program was killed in part by the fact thatMicrosoft never supported the processor. Engineers working on the PowerPC 615 would later find their way toTransmeta, where they worked on theCrusoe processor. With progress having been demonstrated in the development of dynamic translation software, such as Digital'sFX!32 technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.^[39]: 94

"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "RS64". The designation "PowerPC 625" was never used for the final processors.

"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify thePOWER andPowerPC instruction sets. It was later renamed "POWER3", probably to distinguish it from the more consumer oriented "PowerPC" processors used byApple.

"PowerPC 641", codenameHabanero, is a defunct PowerPC project by IBM in the 1994–96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor.^[40][41]

• PowerPC 970
• IBM POWER architecture
• IBM Power microprocessors
• Power ISA
• List of Mac models grouped by CPU type

• Weiss, Shlomo; Smith, James Edward (1994).POWER and PowerPC. Morgan Kaufmann.ISBN 1558602798. — Relevant parts: Chapter 8 (describes the PowerPC 601), and Chapter 11 (a comparison of the PowerPC 601 and Alpha 21064)

• PPC 600 at mackido.com

• PowerPC microprocessors
• IBM microprocessors
• Motorola microprocessors
• Superscalar microprocessors
• 32-bit microprocessors

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