Phase-change memory (also known asPCM,PCME,PRAM,PCRAM,OUM (ovonic unified memory) andC-RAM orCRAM (chalcogenide RAM)) is a type ofnon-volatile random-access memory. PRAMs exploit the unique behaviour ofchalcogenide glass. In PCM, heat produced by the passage of anelectric current through aheating element generally made oftitanium nitride is used to either quickly heat andquench the glass, making itamorphous, or to hold it in its crystallization temperature range for some time, thereby switching it to acrystalline state.[1] PCM also has the ability to achieve a number of distinct intermediary states, thereby having the ability to hold multiplebits in a single cell,[2] but the difficulties in programming cells in this way has prevented these capabilities from being implemented in other technologies (most notablyflash memory) with the same capability.
Recent research on PCM has been directed towards attempting to find viable material alternatives to thephase-change materialGe2Sb2Te5 (GST), with mixed success. Other research has focused on the development of aGeTe–Sb2Te3superlattice to achieve non-thermalphase changes by changing the co-ordination state of the germanium atoms with alaser pulse. This new Interfacial Phase-Change Memory (IPCM) has had many successes and continues to be the site of much active research.[3]
Leon Chua has argued that all two-terminalnon-volatile-memory devices, including PCM, should be consideredmemristors.[4]Stan Williams ofHP Labs has also argued that PCM should be considered a memristor.[5] However, this terminology has been challenged, and the potential applicability of memristor theory to any physically realizable device is open to question.[6][7]
In the 1960s,Stanford R. Ovshinsky ofEnergy Conversion Devices first explored the properties ofchalcogenide glasses as a potential memory technology. In 1969, Charles Sie published a dissertation atIowa State University that both described and demonstrated the feasibility of a phase-change-memory device by integratingchalcogenide film with adiode array.[8][9] A cinematographic study in 1970 established that the phase-change-memory mechanism in chalcogenide glass involveselectric-field-inducedcrystalline filament growth.[10][11] In the September 1970 issue ofElectronics,Gordon Moore, co-founder ofIntel, published an article on the technology.[12] However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed asflash andDRAM memory technologies are expected to encounter scaling difficulties as chiplithography shrinks.[13]
Thecrystalline andamorphous states of chalcogenide glass have dramatically differentelectrical resistivity values. The amorphous, high resistance state represents abinary 0, while the crystalline, low resistance state represents a 1.[citation needed] Chalcogenide is the same material used in re-writableoptical media (such asCD-RW andDVD-RW). In those instances, the material's optical properties are manipulated, rather than its electrical resistivity, as chalcogenide'srefractive index also changes with the state of the material.
Although PRAM has not yet reached the commercialization stage for consumer electronic devices, nearly all prototype devices make use of achalcogenide alloy ofgermanium (Ge),antimony (Sb) andtellurium (Te) calledGeSbTe (GST). Thestoichiometry, or Ge:Sb:Te element ratio, is 2:2:5 in GST. When GST is heated to a high temperature (over 600 °C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state[14] and itselectrical resistance is high. By heating the chalcogenide to a temperature above itscrystallization point, but below themelting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. A crystallization time scale on the order of 100 ns is commonly used.[15] This is longer than conventional volatile memory devices like modernDRAM, which have a switching time on the order of two nanoseconds. However, a January 2006Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds.
A 2008 advance pioneered byIntel andST Microelectronics allowed the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states: the previous amorphous or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent twobits, doublingmemory density.[16]
Phase-change memory devices based ongermanium,antimony andtellurium present manufacturing challenges, since etching and polishing of the material withchalcogens can change the material's composition. Materials based onaluminum and antimony are more thermally stable thanGeSbTe.Al50Sb50 has three distinct resistance levels, offering the potential to store three bits of data in two cells as opposed to two (nine states possible for the pair of cells, using eight of those states yields log2 8 = 3 bits).[17][18]
PRAM's switching time and inherent scalability[19] make it more appealing thanflash memory. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.
Flash memory works by modulating charge (electrons) stored within the gate of aMOS transistor. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or ininsulator "traps"). The presence of charge within the gate shifts the transistor'sthreshold voltage higher or lower, corresponding to a change in the cell'sbit state from 1 to 0 or 0 to 1. Changing the bit's state requires removing the accumulated charge, which demands a relatively largevoltage to "suck" the electrons off the floating gate. This burst of voltage is provided by acharge pump, which takes some time to build up power. General write times for common flash devices are on the order of 100 μs (for a block of data), about 10,000 times the typical 10 ns read time forSRAM for example (for abyte).[citation needed]
PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times faster than conventionalhard drives, makes it particularly interesting innonvolatile memory roles that are currently performance-limited by memory access timing.
In addition, with flash, each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are rated for, currently, only 5,000 writes per sector, and manyflash controllers performwear leveling to spread writes across many physical sectors.
PRAM devices also degrade with use, for different reasons than flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.[20] PRAM lifetime is limited by mechanisms such as degradation due toGSTthermal expansion during programming, metal (and other material) migration, and other mechanisms still unknown.
Flash parts can be programmed before beingsoldered onto aboard, or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (seereflow soldering orwave soldering). This was made worse by the requirement to havelead-free manufacturing requiring higher soldering temperatures. A manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.
The special gates used in flash memory "leak" charge (electrons) over time, causing corruption and loss of data. Theresistivity of the memory element in PRAM is more stable; at the normal working temperature of 85 °C, it is projected to retain data for 300 years.[21]
By carefully modulating the amount of charge stored on the gate, flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles thememory density, reducing cost. PRAM devices originally stored only a single bit in each cell, butIntel's recent advances have removed this problem.[citation needed]
Because flash devices trap electrons to store information, they are susceptible to data corruption fromradiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.
PRAM cell selectors can use various devices:diodes,BJTs andMOSFETs. Using a diode or a BJT provides the greatest amount ofcurrent for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption.Chalcogenide resistance is necessarily larger than that of a diode, meaning operating voltage must exceed 1 V by a wide margin to guarantee adequateforward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the totalreverse bias leakage current from the unselected bit lines. Intransistor-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discretedopants as thep-n junction width scales down.Thin film-based selectors allow higher densities, utilizing < 4 F2 cell area by stacking memory layers horizontally or vertically. Often the isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Chalcogenide-based threshold switches have been demonstrated as a viable selector for high-density PCM arrays[22]
In August 2004, Nanochip licensed PRAM technology for use inMEMS (micro-electric-mechanical-systems) probe storage devices. These devices are notsolid state. Instead, a very small platter coated inchalcogenide is dragged beneath thousands or even millions of electrical probes that can read and write the chalcogenide.Hewlett-Packard's micro-mover technology can accurately position the platter to 3 nm so densities of more than 1 Tbit (125 GB) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach resemblesIBM'sMillipede technology.
In September 2006,Samsung announced a prototype 512 Mb (64 MB) device usingdiode switches.[23] The announcement was something of a surprise, and it was especially notable for its fairly highmemory density. The prototype featured a cell size of only 46.7 nm, smaller than commercialflash devices available at the time. Although flash devices of highercapacity were available (64 Gb, or 8 GB, was just coming to market), other technologies competing to replace flash in general offered lower densities (larger cell sizes). The only productionMRAM andFeRAM devices are only 4 Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potentialreplacement for NOR flash, where device capacities typically lag behind those ofNAND flash devices. State-of-the-art capacities on NAND passed 512 Mb some time ago.NOR flash offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time).
Samsung's announcement was followed by one fromIntel andSTMicroelectronics, who demonstrated their own PRAM devices at the 2006Intel Developer Forum in October.[24] They showed a 128 Mb part that began manufacture at STMicroelectronics's research lab in Agrate, Italy. Intel stated that the devices were strictlyproof-of-concept.
PRAM is also a promising technology in the military and aerospace industries where radiation effects make the use of standardnon-volatile memories such as flash impractical. PRAM devices have been introduced byBAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) andlatchup immunity. In addition, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacingPROMs andEEPROMs in space systems.
In February 2008, Intel and STMicroelectronics revealed the first multilevel (MLC) PRAM array prototype. The prototype stored two logical bits in each physical cell, in effect 256 Mb of memory stored in a 128 Mb physical array. This means that instead of the normal two states—fullyamorphous and fullycrystalline—an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area.[16] In June 2011,[25] IBM announced that they had created stable, reliable, multi-bit phase-change memory with high performance and stability.SK Hynix had a joint developmental agreement and a technology license agreement with IBM for the development of multi-level PRAM technology.[26]
Also in February 2008, Intel and STMicroelectronics shipped prototype samples of their first PRAM product to customers. The 90 nm, 128 Mb (16 MB) product was called Alverstone.[27]
In June 2009, Samsung andNumonyx B.V. announced a collaborative effort in the development of PRAM market-tailored hardware products.[28]
In April 2010,[29] Numonyx announced the Omneo line of 128-Mbit NOR-compatible phase-change memories. Samsung announced shipment of 512 Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010.
In December 2018 STMicroelectronics presented design and performance data for a 16 MB ePCM array for a 28 nm fully depletedsilicon on insulator automotive control unit.[30]
More recently, there is significant interest in the application of PCM for in-memory computing.[31] The essential idea is to perform computational tasks such asmatrix-vector-multiply operations in the memory array itself by exploiting PCM's analog storage capability andKirchhoff's circuit laws. PCM-based in-memory computing could be interesting for applications such asdeep learninginference which do not require very high computing precision.[32] In 2021, IBM published a full-fledged in-memory computing core based on multi-level PCM integrated in 14 nmCMOS technology node.[33]
The greatest challenge for phase-change memory has been the requirement of high programmingcurrent density (>107 A/cm2, compared to 105...106 A/cm2 for a typicaltransistor ordiode).[citation needed]The contact between the hot phase-change region and the adjacentdielectric is another fundamental concern. The dielectric may begin to leakcurrent at higher temperature, or may loseadhesion when expanding at a different rate from the phase-change material.
Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions that allow for fastcrystallization should not be too similar to standby conditions, e.g. room temperature, otherwise data retention cannot be sustained. With the properactivation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.
Probably the biggest challenge for phase-change memory is its long-termresistance andthreshold voltage drift.[34] The resistance of theamorphous state slowly increases according to apower law (~t0.1). This severely limits the ability for multilevel operation, since a lower intermediate state would be confused with a higher intermediate state at a later time, and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.
In April 2010,Numonyx released its Omneo line of parallel and serial interface 128 MbNOR flash replacement PRAM chips. Although the NOR flash chips they intended to replace operated in the −40-85 °C range, the PRAM chips operated in the 0-70 °C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature-sensitivep–n junctions to provide the high currents needed for programming.
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