PWRficient is amicroprocessor series byP.A. Semi where thePA6T-1682M was the only one that became an actual product.

PWRficient processors comply with the64-bitPower ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined tomulti-coresystem-on-a-chip (SoC) designs, combiningCPU,northbridge, andsouthbridge functionality on a single processordie.

The PA6T is the first and only processor core from P.A. Semi, in two distinct product lines:16xxM dual core and13xxM/E single core. The PA6T lines differed inL2 cache size,memory controllers, communication functionality, and cryptography offloading features. P.A. Semi planned up to 16 cores.^[1]

The PA6T is the first Power ISA core designed from scratch in the previous ten years outside theAIM alliance, which includedIBM,Motorola,Freescale, andApple Inc. SinceTexas Instruments was an investors in P.A. Semi, it was suggested that its fabrication plants would have manufactured the PWRficient processors.^[1]

PWRficient processors were initially shipped to select customers in February 2007 and were released worldwide in Q4 2007.^[2]

P.A. Semi was bought byApple Inc. in April 2008,^[3] and closed development of PWRficient architecture processors. However, it will continue to manufacture, sell, and support these components for the foreseeable future due to an agreement with theUS Government for some military applications.^[4][5] Some components of the P.A. Semi PWRficient were later integrated intoApple silicon.^[6]

PA6T-1682M

General information
Launched	2007
Discontinued	2008
Designed by	P.A. Semi
Performance
Max.CPUclock rate	1.8 GHz to 2.0 GHz
Cache
L1cache	64+64 KB/core
L2 cache	2 MB/core
Architecture and classification
Technology node	65 nm
Microarchitecture	PA6T
Instruction set	Power ISA (Power ISA v.2.04)
Physical specifications
Cores	2

PWRficient processors comprise three parts:

PA6T

• Superscalar,out-of-order32-bit/64-bitPower ISA processor core
• Adheres to thePower ISA v.2.04
• Little endian or big endian operation
• 64/64 kB instruction and dataL1 caches. 32 GB/s bandwidth.
• Sixexecution units including adouble precisionFPU andAltiVec unit
• Hypervisor andvirtualization support
• Maximum 7 W at 2 GHz
• 11 million transistors, 10 mm² large @ 65 nm.

CONEXIUM

• scalable cross-bar interconnect
• 1–8SMP cores
• 1–2L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
• 1–4 1067 MHzDDR2memory controllers. 16 GB/s bandwidth.
• 64 GB/s peak bandwidth
• MOESI coherency

ENVOI

• CentralizedDMA engine, 32 GB/s bandwidth
• 16–64SerDes lanes
• XAUI
• PCI Express
• SGMII
• Offload engine forcryptography,RAID,TCP

• Curtiss-Wright planned the 1682M processor for itssignal processing systems.^[7]
• Mercury Computer Systems planned the 1682M processor for itssignal andimage processing systems.^[8]
• NEC planned the 1682M processor for itsstorage array systems.^[9]
• AmigaOne X1000 has the 1682M processor as CPU.^[10]

• "Start-up plans new energy-efficient processor". Archived from the original on 2013-01-02. Retrieved2006-11-24.{{cite web}}: CS1 maint: bot: original URL status unknown (link)
• PA Semi attacks performance/Watt
• FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies
• Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design

• Power microprocessors

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